1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2017 Marek Behun <marek.behun (at) nic.cz> 4 * Copyright (C) 2016 Tomas Hlavacek <tomas.hlavacek (at) nic.cz> 5 * 6 * Derived from the code for 7 * Marvell/db-88f6820-gp by Stefan Roese <sr (at) denx.de> 8 */ 9 10 #include <common.h> 11 #include <environment.h> 12 #include <i2c.h> 13 #include <miiphy.h> 14 #include <netdev.h> 15 #include <asm/io.h> 16 #include <asm/arch/cpu.h> 17 #include <asm/arch/soc.h> 18 #include <dm/uclass.h> 19 #include <fdt_support.h> 20 #include <time.h> 21 22 #ifdef CONFIG_ATSHA204A 23 # include <atsha204a-i2c.h> 24 #endif 25 26 #ifdef CONFIG_WDT_ORION 27 # include <wdt.h> 28 #endif 29 30 #include "../drivers/ddr/marvell/a38x/ddr3_init.h" 31 #include <../serdes/a38x/high_speed_env_spec.h> 32 33 DECLARE_GLOBAL_DATA_PTR; 34 35 #define OMNIA_I2C_EEPROM_DM_NAME "i2c@0" 36 #define OMNIA_I2C_EEPROM 0x54 37 #define OMNIA_I2C_EEPROM_CONFIG_ADDR 0x0 38 #define OMNIA_I2C_EEPROM_ADDRLEN 2 39 #define OMNIA_I2C_EEPROM_MAGIC 0x0341a034 40 41 #define OMNIA_I2C_MCU_DM_NAME "i2c@0" 42 #define OMNIA_I2C_MCU_ADDR_STATUS 0x1 43 #define OMNIA_I2C_MCU_SATA 0x20 44 #define OMNIA_I2C_MCU_CARDDET 0x10 45 #define OMNIA_I2C_MCU 0x2a 46 #define OMNIA_I2C_MCU_WDT_ADDR 0x0b 47 48 #define OMNIA_ATSHA204_OTP_VERSION 0 49 #define OMNIA_ATSHA204_OTP_SERIAL 1 50 #define OMNIA_ATSHA204_OTP_MAC0 3 51 #define OMNIA_ATSHA204_OTP_MAC1 4 52 53 #define MVTWSI_ARMADA_DEBUG_REG 0x8c 54 55 /* 56 * Those values and defines are taken from the Marvell U-Boot version 57 * "u-boot-2013.01-2014_T3.0" 58 */ 59 #define OMNIA_GPP_OUT_ENA_LOW \ 60 (~(BIT(1) | BIT(4) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | \ 61 BIT(10) | BIT(11) | BIT(19) | BIT(22) | BIT(23) | BIT(25) | \ 62 BIT(26) | BIT(27) | BIT(29) | BIT(30) | BIT(31))) 63 #define OMNIA_GPP_OUT_ENA_MID \ 64 (~(BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(15) | \ 65 BIT(16) | BIT(17) | BIT(18))) 66 67 #define OMNIA_GPP_OUT_VAL_LOW 0x0 68 #define OMNIA_GPP_OUT_VAL_MID 0x0 69 #define OMNIA_GPP_POL_LOW 0x0 70 #define OMNIA_GPP_POL_MID 0x0 71 72 static struct serdes_map board_serdes_map_pex[] = { 73 {PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0}, 74 {USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}, 75 {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0}, 76 {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}, 77 {PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0}, 78 {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0} 79 }; 80 81 static struct serdes_map board_serdes_map_sata[] = { 82 {SATA0, SERDES_SPEED_6_GBPS, SERDES_DEFAULT_MODE, 0, 0}, 83 {USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}, 84 {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0}, 85 {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}, 86 {PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0}, 87 {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0} 88 }; 89 90 static bool omnia_detect_sata(void) 91 { 92 struct udevice *bus, *dev; 93 int ret, retry = 3; 94 u16 mode; 95 96 puts("SERDES0 card detect: "); 97 98 if (uclass_get_device_by_name(UCLASS_I2C, OMNIA_I2C_MCU_DM_NAME, &bus)) { 99 puts("Cannot find MCU bus!\n"); 100 return false; 101 } 102 103 ret = i2c_get_chip(bus, OMNIA_I2C_MCU, 1, &dev); 104 if (ret) { 105 puts("Cannot get MCU chip!\n"); 106 return false; 107 } 108 109 for (; retry > 0; --retry) { 110 ret = dm_i2c_read(dev, OMNIA_I2C_MCU_ADDR_STATUS, (uchar *) &mode, 2); 111 if (!ret) 112 break; 113 } 114 115 if (!retry) { 116 puts("I2C read failed! Default PEX\n"); 117 return false; 118 } 119 120 if (!(mode & OMNIA_I2C_MCU_CARDDET)) { 121 puts("NONE\n"); 122 return false; 123 } 124 125 if (mode & OMNIA_I2C_MCU_SATA) { 126 puts("SATA\n"); 127 return true; 128 } else { 129 puts("PEX\n"); 130 return false; 131 } 132 } 133 134 int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count) 135 { 136 if (omnia_detect_sata()) { 137 *serdes_map_array = board_serdes_map_sata; 138 *count = ARRAY_SIZE(board_serdes_map_sata); 139 } else { 140 *serdes_map_array = board_serdes_map_pex; 141 *count = ARRAY_SIZE(board_serdes_map_pex); 142 } 143 144 return 0; 145 } 146 147 struct omnia_eeprom { 148 u32 magic; 149 u32 ramsize; 150 char region[4]; 151 u32 crc; 152 }; 153 154 static bool omnia_read_eeprom(struct omnia_eeprom *oep) 155 { 156 struct udevice *bus, *dev; 157 int ret, crc, retry = 3; 158 159 if (uclass_get_device_by_name(UCLASS_I2C, OMNIA_I2C_EEPROM_DM_NAME, &bus)) { 160 puts("Cannot find EEPROM bus\n"); 161 return false; 162 } 163 164 ret = i2c_get_chip(bus, OMNIA_I2C_EEPROM, OMNIA_I2C_EEPROM_ADDRLEN, &dev); 165 if (ret) { 166 puts("Cannot get EEPROM chip\n"); 167 return false; 168 } 169 170 for (; retry > 0; --retry) { 171 ret = dm_i2c_read(dev, OMNIA_I2C_EEPROM_CONFIG_ADDR, (uchar *) oep, sizeof(struct omnia_eeprom)); 172 if (ret) 173 continue; 174 175 if (oep->magic != OMNIA_I2C_EEPROM_MAGIC) { 176 puts("I2C EEPROM missing magic number!\n"); 177 continue; 178 } 179 180 crc = crc32(0, (unsigned char *) oep, 181 sizeof(struct omnia_eeprom) - 4); 182 if (crc == oep->crc) { 183 break; 184 } else { 185 printf("CRC of EEPROM memory config failed! " 186 "calc=0x%04x saved=0x%04x\n", crc, oep->crc); 187 } 188 } 189 190 if (!retry) { 191 puts("I2C EEPROM read failed!\n"); 192 return false; 193 } 194 195 return true; 196 } 197 198 /* 199 * Define the DDR layout / topology here in the board file. This will 200 * be used by the DDR3 init code in the SPL U-Boot version to configure 201 * the DDR3 controller. 202 */ 203 static struct mv_ddr_topology_map board_topology_map_1g = { 204 DEBUG_LEVEL_ERROR, 205 0x1, /* active interfaces */ 206 /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */ 207 { { { {0x1, 0, 0, 0}, 208 {0x1, 0, 0, 0}, 209 {0x1, 0, 0, 0}, 210 {0x1, 0, 0, 0}, 211 {0x1, 0, 0, 0} }, 212 SPEED_BIN_DDR_1600K, /* speed_bin */ 213 MV_DDR_DEV_WIDTH_16BIT, /* memory_width */ 214 MV_DDR_DIE_CAP_4GBIT, /* mem_size */ 215 DDR_FREQ_800, /* frequency */ 216 0, 0, /* cas_wl cas_l */ 217 MV_DDR_TEMP_NORMAL, /* temperature */ 218 MV_DDR_TIM_2T} }, /* timing */ 219 BUS_MASK_32BIT, /* Busses mask */ 220 MV_DDR_CFG_DEFAULT, /* ddr configuration data source */ 221 { {0} }, /* raw spd data */ 222 {0} /* timing parameters */ 223 }; 224 225 static struct mv_ddr_topology_map board_topology_map_2g = { 226 DEBUG_LEVEL_ERROR, 227 0x1, /* active interfaces */ 228 /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */ 229 { { { {0x1, 0, 0, 0}, 230 {0x1, 0, 0, 0}, 231 {0x1, 0, 0, 0}, 232 {0x1, 0, 0, 0}, 233 {0x1, 0, 0, 0} }, 234 SPEED_BIN_DDR_1600K, /* speed_bin */ 235 MV_DDR_DEV_WIDTH_16BIT, /* memory_width */ 236 MV_DDR_DIE_CAP_8GBIT, /* mem_size */ 237 DDR_FREQ_800, /* frequency */ 238 0, 0, /* cas_wl cas_l */ 239 MV_DDR_TEMP_NORMAL, /* temperature */ 240 MV_DDR_TIM_2T} }, /* timing */ 241 BUS_MASK_32BIT, /* Busses mask */ 242 MV_DDR_CFG_DEFAULT, /* ddr configuration data source */ 243 { {0} }, /* raw spd data */ 244 {0} /* timing parameters */ 245 }; 246 247 struct mv_ddr_topology_map *mv_ddr_topology_map_get(void) 248 { 249 static int mem = 0; 250 struct omnia_eeprom oep; 251 252 /* Get the board config from EEPROM */ 253 if (mem == 0) { 254 if(!omnia_read_eeprom(&oep)) 255 goto out; 256 257 printf("Memory config in EEPROM: 0x%02x\n", oep.ramsize); 258 259 if (oep.ramsize == 0x2) 260 mem = 2; 261 else 262 mem = 1; 263 } 264 265 out: 266 /* Hardcoded fallback */ 267 if (mem == 0) { 268 puts("WARNING: Memory config from EEPROM read failed.\n"); 269 puts("Falling back to default 1GiB map.\n"); 270 mem = 1; 271 } 272 273 /* Return the board topology as defined in the board code */ 274 if (mem == 1) 275 return &board_topology_map_1g; 276 if (mem == 2) 277 return &board_topology_map_2g; 278 279 return &board_topology_map_1g; 280 } 281 282 #ifndef CONFIG_SPL_BUILD 283 static int set_regdomain(void) 284 { 285 struct omnia_eeprom oep; 286 char rd[3] = {' ', ' ', 0}; 287 288 if (omnia_read_eeprom(&oep)) 289 memcpy(rd, &oep.region, 2); 290 else 291 puts("EEPROM regdomain read failed.\n"); 292 293 printf("Regdomain set to %s\n", rd); 294 return env_set("regdomain", rd); 295 } 296 #endif 297 298 int board_early_init_f(void) 299 { 300 u32 i2c_debug_reg; 301 302 /* Configure MPP */ 303 writel(0x11111111, MVEBU_MPP_BASE + 0x00); 304 writel(0x11111111, MVEBU_MPP_BASE + 0x04); 305 writel(0x11244011, MVEBU_MPP_BASE + 0x08); 306 writel(0x22222111, MVEBU_MPP_BASE + 0x0c); 307 writel(0x22200002, MVEBU_MPP_BASE + 0x10); 308 writel(0x30042022, MVEBU_MPP_BASE + 0x14); 309 writel(0x55550555, MVEBU_MPP_BASE + 0x18); 310 writel(0x00005550, MVEBU_MPP_BASE + 0x1c); 311 312 /* Set GPP Out value */ 313 writel(OMNIA_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00); 314 writel(OMNIA_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00); 315 316 /* Set GPP Polarity */ 317 writel(OMNIA_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c); 318 writel(OMNIA_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c); 319 320 /* Set GPP Out Enable */ 321 writel(OMNIA_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04); 322 writel(OMNIA_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04); 323 324 /* 325 * Disable I2C debug mode blocking 0x64 I2C address. 326 * Note: that would be redundant once Turris Omnia migrates to DM_I2C, 327 * because the mvtwsi driver includes equivalent code. 328 */ 329 i2c_debug_reg = readl(MVEBU_TWSI_BASE + MVTWSI_ARMADA_DEBUG_REG); 330 i2c_debug_reg &= ~(1<<18); 331 writel(i2c_debug_reg, MVEBU_TWSI_BASE + MVTWSI_ARMADA_DEBUG_REG); 332 333 return 0; 334 } 335 336 #ifndef CONFIG_SPL_BUILD 337 static bool disable_mcu_watchdog(void) 338 { 339 struct udevice *bus, *dev; 340 int ret, retry = 3; 341 uchar buf[1] = {0x0}; 342 343 if (uclass_get_device_by_name(UCLASS_I2C, OMNIA_I2C_MCU_DM_NAME, &bus)) { 344 puts("Cannot find MCU bus! Can not disable MCU WDT.\n"); 345 return false; 346 } 347 348 ret = i2c_get_chip(bus, OMNIA_I2C_MCU, 1, &dev); 349 if (ret) { 350 puts("Cannot get MCU chip! Can not disable MCU WDT.\n"); 351 return false; 352 } 353 354 for (; retry > 0; --retry) 355 if (!dm_i2c_write(dev, OMNIA_I2C_MCU_WDT_ADDR, (uchar *) buf, 1)) 356 break; 357 358 if (retry <= 0) { 359 puts("I2C MCU watchdog failed to disable!\n"); 360 return false; 361 } 362 363 return true; 364 } 365 #endif 366 367 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT_ORION) 368 static struct udevice *watchdog_dev = NULL; 369 #endif 370 371 int board_init(void) 372 { 373 /* adress of boot parameters */ 374 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; 375 376 #ifndef CONFIG_SPL_BUILD 377 # ifdef CONFIG_WDT_ORION 378 if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) { 379 puts("Cannot find Armada 385 watchdog!\n"); 380 } else { 381 puts("Enabling Armada 385 watchdog.\n"); 382 wdt_start(watchdog_dev, (u32) 25000000 * 120, 0); 383 } 384 # endif 385 386 if (disable_mcu_watchdog()) 387 puts("Disabled MCU startup watchdog.\n"); 388 389 set_regdomain(); 390 #endif 391 392 return 0; 393 } 394 395 #ifdef CONFIG_WATCHDOG 396 /* Called by macro WATCHDOG_RESET */ 397 void watchdog_reset(void) 398 { 399 # if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT_ORION) 400 static ulong next_reset = 0; 401 ulong now; 402 403 if (!watchdog_dev) 404 return; 405 406 now = timer_get_us(); 407 408 /* Do not reset the watchdog too often */ 409 if (now > next_reset) { 410 wdt_reset(watchdog_dev); 411 next_reset = now + 1000; 412 } 413 # endif 414 } 415 #endif 416 417 int board_late_init(void) 418 { 419 #ifndef CONFIG_SPL_BUILD 420 set_regdomain(); 421 #endif 422 423 return 0; 424 } 425 426 #ifdef CONFIG_ATSHA204A 427 static struct udevice *get_atsha204a_dev(void) 428 { 429 static struct udevice *dev = NULL; 430 431 if (dev != NULL) 432 return dev; 433 434 if (uclass_get_device_by_name(UCLASS_MISC, "atsha204a@64", &dev)) { 435 puts("Cannot find ATSHA204A on I2C bus!\n"); 436 dev = NULL; 437 } 438 439 return dev; 440 } 441 #endif 442 443 int checkboard(void) 444 { 445 u32 version_num, serial_num; 446 int err = 1; 447 448 #ifdef CONFIG_ATSHA204A 449 struct udevice *dev = get_atsha204a_dev(); 450 451 if (dev) { 452 err = atsha204a_wakeup(dev); 453 if (err) 454 goto out; 455 456 err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false, 457 OMNIA_ATSHA204_OTP_VERSION, 458 (u8 *) &version_num); 459 if (err) 460 goto out; 461 462 err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false, 463 OMNIA_ATSHA204_OTP_SERIAL, 464 (u8 *) &serial_num); 465 if (err) 466 goto out; 467 468 atsha204a_sleep(dev); 469 } 470 471 out: 472 #endif 473 474 if (err) 475 printf("Board: Turris Omnia (ver N/A). SN: N/A\n"); 476 else 477 printf("Board: Turris Omnia SNL %08X%08X\n", 478 be32_to_cpu(version_num), be32_to_cpu(serial_num)); 479 480 return 0; 481 } 482 483 static void increment_mac(u8 *mac) 484 { 485 int i; 486 487 for (i = 5; i >= 3; i--) { 488 mac[i] += 1; 489 if (mac[i]) 490 break; 491 } 492 } 493 494 int misc_init_r(void) 495 { 496 #ifdef CONFIG_ATSHA204A 497 int err; 498 struct udevice *dev = get_atsha204a_dev(); 499 u8 mac0[4], mac1[4], mac[6]; 500 501 if (!dev) 502 goto out; 503 504 err = atsha204a_wakeup(dev); 505 if (err) 506 goto out; 507 508 err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false, 509 OMNIA_ATSHA204_OTP_MAC0, mac0); 510 if (err) 511 goto out; 512 513 err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false, 514 OMNIA_ATSHA204_OTP_MAC1, mac1); 515 if (err) 516 goto out; 517 518 atsha204a_sleep(dev); 519 520 mac[0] = mac0[1]; 521 mac[1] = mac0[2]; 522 mac[2] = mac0[3]; 523 mac[3] = mac1[1]; 524 mac[4] = mac1[2]; 525 mac[5] = mac1[3]; 526 527 if (is_valid_ethaddr(mac)) 528 eth_env_set_enetaddr("ethaddr", mac); 529 530 increment_mac(mac); 531 532 if (is_valid_ethaddr(mac)) 533 eth_env_set_enetaddr("eth1addr", mac); 534 535 increment_mac(mac); 536 537 if (is_valid_ethaddr(mac)) 538 eth_env_set_enetaddr("eth2addr", mac); 539 540 out: 541 #endif 542 543 return 0; 544 } 545 546
