1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2013 Boundary Devices 4 * 5 * Device Configuration Data (DCD) 6 * 7 * Each entry must have the format: 8 * Addr-type Address Value 9 * 10 * where: 11 * Addr-type register length (1,2 or 4 bytes) 12 * Address absolute address of the register 13 * value value to be stored in the register 14 */ 15 16 /* DDR IO TYPE */ 17 DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 18 DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 19 /* Clock */ 20 DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00000030 21 DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00000030 22 /* Address */ 23 DATA 4, MX6_IOM_DRAM_CAS, 0x00000030 24 DATA 4, MX6_IOM_DRAM_RAS, 0x00000030 25 DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 26 /* Control */ 27 DATA 4, MX6_IOM_DRAM_RESET, 0x00000030 28 DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 29 DATA 4, MX6_IOM_DRAM_SDODT0, 0x00000030 30 DATA 4, MX6_IOM_DRAM_SDODT1, 0x00000030 31 DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 32 /* Data Strobe */ 33 DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 34 DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000028 35 DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000028 36 DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000028 37 DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000028 38 DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000028 39 DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000028 40 DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000028 41 DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000028 42 DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 43 DATA 4, MX6_IOM_GRP_B0DS, 0x00000028 44 DATA 4, MX6_IOM_GRP_B1DS, 0x00000028 45 DATA 4, MX6_IOM_GRP_B2DS, 0x00000028 46 DATA 4, MX6_IOM_GRP_B3DS, 0x00000028 47 DATA 4, MX6_IOM_GRP_B4DS, 0x00000028 48 DATA 4, MX6_IOM_GRP_B5DS, 0x00000028 49 DATA 4, MX6_IOM_GRP_B6DS, 0x00000028 50 DATA 4, MX6_IOM_GRP_B7DS, 0x00000028 51 DATA 4, MX6_IOM_DRAM_DQM0, 0x00000028 52 DATA 4, MX6_IOM_DRAM_DQM1, 0x00000028 53 DATA 4, MX6_IOM_DRAM_DQM2, 0x00000028 54 DATA 4, MX6_IOM_DRAM_DQM3, 0x00000028 55 DATA 4, MX6_IOM_DRAM_DQM4, 0x00000028 56 DATA 4, MX6_IOM_DRAM_DQM5, 0x00000028 57 DATA 4, MX6_IOM_DRAM_DQM6, 0x00000028 58 DATA 4, MX6_IOM_DRAM_DQM7, 0x00000028 59
