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      1 // SPDX-License-Identifier: GPL-2.0+
      2 /*
      3  * Bluegiga APX4 Development Kit
      4  *
      5  * Copyright (C) 2012 Bluegiga Technologies Oy
      6  *
      7  * Authors:
      8  * Veli-Pekka Peltola <veli-pekka.peltola (at) bluegiga.com>
      9  * Lauri Hintsala <lauri.hintsala (at) bluegiga.com>
     10  *
     11  * Based on spl_boot.c:
     12  * Copyright (C) 2011 Marek Vasut <marek.vasut (at) gmail.com>
     13  * on behalf of DENX Software Engineering GmbH
     14  */
     15 
     16 #include <common.h>
     17 #include <config.h>
     18 #include <asm/gpio.h>
     19 #include <asm/io.h>
     20 #include <asm/arch/iomux-mx28.h>
     21 #include <asm/arch/imx-regs.h>
     22 #include <asm/arch/sys_proto.h>
     23 
     24 #define	MUX_CONFIG_SSP0	(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
     25 #define	MUX_CONFIG_GPMI	(MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
     26 #define	MUX_CONFIG_ENET	(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
     27 #define	MUX_CONFIG_EMI	(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL)
     28 
     29 const iomux_cfg_t iomux_setup[] = {
     30 	/* DUART */
     31 	MX28_PAD_PWM0__DUART_RX,
     32 	MX28_PAD_PWM1__DUART_TX,
     33 
     34 	/* LED */
     35 	MX28_PAD_PWM3__GPIO_3_28,
     36 
     37 	/* MMC0 */
     38 	MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0,
     39 	MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0,
     40 	MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0,
     41 	MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0,
     42 	MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0,
     43 	MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT |
     44 		(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_NOPULL),
     45 	MX28_PAD_SSP0_SCK__SSP0_SCK |
     46 		(MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
     47 
     48 	/* GPMI NAND */
     49 	MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_GPMI,
     50 	MX28_PAD_GPMI_D01__GPMI_D1 | MUX_CONFIG_GPMI,
     51 	MX28_PAD_GPMI_D02__GPMI_D2 | MUX_CONFIG_GPMI,
     52 	MX28_PAD_GPMI_D03__GPMI_D3 | MUX_CONFIG_GPMI,
     53 	MX28_PAD_GPMI_D04__GPMI_D4 | MUX_CONFIG_GPMI,
     54 	MX28_PAD_GPMI_D05__GPMI_D5 | MUX_CONFIG_GPMI,
     55 	MX28_PAD_GPMI_D06__GPMI_D6 | MUX_CONFIG_GPMI,
     56 	MX28_PAD_GPMI_D07__GPMI_D7 | MUX_CONFIG_GPMI,
     57 	MX28_PAD_GPMI_CE0N__GPMI_CE0N | MUX_CONFIG_GPMI,
     58 	MX28_PAD_GPMI_RDY0__GPMI_READY0 | MUX_CONFIG_GPMI,
     59 	MX28_PAD_GPMI_RDN__GPMI_RDN |
     60 		(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP),
     61 	MX28_PAD_GPMI_WRN__GPMI_WRN | MUX_CONFIG_GPMI,
     62 	MX28_PAD_GPMI_ALE__GPMI_ALE | MUX_CONFIG_GPMI,
     63 	MX28_PAD_GPMI_CLE__GPMI_CLE | MUX_CONFIG_GPMI,
     64 	MX28_PAD_GPMI_RESETN__GPMI_RESETN | MUX_CONFIG_GPMI,
     65 
     66 	/* FEC0 */
     67 	MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET,
     68 	MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET,
     69 	MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET,
     70 	MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET,
     71 	MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET,
     72 	MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET,
     73 	MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET,
     74 	MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET,
     75 	MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET,
     76 
     77 	/* I2C */
     78 	MX28_PAD_I2C0_SCL__I2C0_SCL,
     79 	MX28_PAD_I2C0_SDA__I2C0_SDA,
     80 
     81 	/* EMI */
     82 	MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI,
     83 	MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI,
     84 	MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI,
     85 	MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI,
     86 	MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI,
     87 	MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI,
     88 	MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI,
     89 	MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI,
     90 	MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI,
     91 	MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI,
     92 	MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI,
     93 	MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI,
     94 	MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI,
     95 	MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI,
     96 	MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI,
     97 	MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI,
     98 	MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI,
     99 	MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,
    100 	MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI,
    101 	MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,
    102 	MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI,
    103 	MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,
    104 	MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,
    105 	MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,
    106 	MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI,
    107 
    108 	MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI,
    109 	MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI,
    110 	MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI,
    111 	MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI,
    112 	MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI,
    113 	MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI,
    114 	MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI,
    115 	MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI,
    116 	MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI,
    117 	MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI,
    118 	MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI,
    119 	MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI,
    120 	MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI,
    121 	MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI,
    122 	MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI,
    123 	MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,
    124 	MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,
    125 	MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI,
    126 	MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,
    127 	MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
    128 	MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
    129 	MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,
    130 	MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI,
    131 	MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,
    132 };
    133 
    134 void board_init_ll(const uint32_t arg, const uint32_t *resptr)
    135 {
    136 	mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup));
    137 
    138 	/* switch LED on */
    139 	gpio_direction_output(MX28_PAD_PWM3__GPIO_3_28, 0);
    140 }
    141 
    142 void mxs_adjust_memory_params(uint32_t *dram_vals)
    143 {
    144 	/*
    145 	 * All address lines are routed from CPU to memory chip.
    146 	 * ADDR_PINS field is set to zero.
    147 	 */
    148 	dram_vals[0x74 >> 2] = 0x0f02000a;
    149 
    150 	/* Used memory has 4 banks. EIGHT_BANK_MODE bit is disabled. */
    151 	dram_vals[0x7c >> 2] = 0x00000101;
    152 }
    153