1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2013 Boundary Devices 4 * 5 * Device Configuration Data (DCD) 6 * 7 * Each entry must have the format: 8 * Addr-type Address Value 9 * 10 * where: 11 * Addr-type register length (1,2 or 4 bytes) 12 * Address absolute address of the register 13 * value value to be stored in the register 14 */ 15 16 /* 17 * DDR3 settings 18 * MX6Q ddr is limited to 1066 Mhz currently 1056 MHz(528 MHz clock), 19 * memory bus width: 64 bits x16/x32/x64 20 * MX6DL ddr is limited to 800 MHz(400 MHz clock) 21 * memory bus width: 64 bits x16/x32/x64 22 * MX6SOLO ddr is limited to 800 MHz(400 MHz clock) 23 * memory bus width: 32 bits x16/x32 24 */ 25 DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 26 DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 27 DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 28 DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 29 DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030 30 DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030 31 DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030 32 DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030 33 34 DATA 4, MX6_IOM_GRP_B0DS, 0x00000030 35 DATA 4, MX6_IOM_GRP_B1DS, 0x00000030 36 DATA 4, MX6_IOM_GRP_B2DS, 0x00000030 37 DATA 4, MX6_IOM_GRP_B3DS, 0x00000030 38 DATA 4, MX6_IOM_GRP_B4DS, 0x00000030 39 DATA 4, MX6_IOM_GRP_B5DS, 0x00000030 40 DATA 4, MX6_IOM_GRP_B6DS, 0x00000030 41 DATA 4, MX6_IOM_GRP_B7DS, 0x00000030 42 DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 43 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ 44 DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 45 46 DATA 4, MX6_IOM_DRAM_DQM0, 0x00020030 47 DATA 4, MX6_IOM_DRAM_DQM1, 0x00020030 48 DATA 4, MX6_IOM_DRAM_DQM2, 0x00020030 49 DATA 4, MX6_IOM_DRAM_DQM3, 0x00020030 50 DATA 4, MX6_IOM_DRAM_DQM4, 0x00020030 51 DATA 4, MX6_IOM_DRAM_DQM5, 0x00020030 52 DATA 4, MX6_IOM_DRAM_DQM6, 0x00020030 53 DATA 4, MX6_IOM_DRAM_DQM7, 0x00020030 54 55 DATA 4, MX6_IOM_DRAM_CAS, 0x00020030 56 DATA 4, MX6_IOM_DRAM_RAS, 0x00020030 57 DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030 58 DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030 59 60 DATA 4, MX6_IOM_DRAM_RESET, 0x00020030 61 DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000 62 DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000 63 64 DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030 65 DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030 66 67 /* (differential input) */ 68 DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 69 /* (differential input) */ 70 DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 71 /* disable ddr pullups */ 72 DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 73 DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 74 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ 75 DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 76 77 /* Read data DQ Byte0-3 delay */ 78 DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 79 DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 80 DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 81 DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 82 DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 83 DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 84 DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 85 DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 86 87 /* 88 * MDMISC mirroring interleaved (row/bank/col) 89 */ 90 DATA 4, MX6_MMDC_P0_MDMISC, 0x00081740 91 92 /* 93 * MDSCR con_req 94 */ 95 DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 96
