Home | History | Annotate | only in /external/u-boot/board/cadence/xtfpga
Up to higher level directory
NameDateSize
Kconfig22-Oct-2020668
MAINTAINERS22-Oct-2020183
Makefile22-Oct-2020106
README22-Oct-20204.7K
xtfpga.c22-Oct-20202.7K

README

      1 		Tensilica 'xtfpga' Evaluation Boards
      2 		====================================
      3 
      4 Tensilica's 'xtfpga' evaluation boards are actually a set of different
      5 boards that share configurations. The following is a list of supported
      6 hardware by this board type:
      7 
      8 - XT-AV60  / LX60
      9 - XT-AV110 / LX110
     10 - XT-AV200 / LX200
     11 - ML605
     12 - KC705
     13 
     14 All boards provide the following common configurations:
     15 
     16 - An Xtensa or Diamond processor core.
     17 - An on-chip-debug (OCD) JTAG interface.
     18 - A 16550 compatible UART and serial port.
     19 - An OpenCores Wishbone 10/100-base-T ethernet interface.
     20 - A 32 char two line LCD display. (except for the LX200)
     21 
     22 LX60/LX110/LX200:
     23 
     24 - Virtex-4 (XC4VLX60 / XCV4LX200) / Virtext-5 (XC5VLX110)
     25 - 128MB / 64MB (LX60) memory
     26 - 16MB / 4MB (LX60) Linear Flash
     27 
     28 ML605
     29 
     30 - Virtex-6 (XC6VLX240T)
     31 - 512MB DDR3 memory
     32 - 16MB Linear BPI Flash
     33 
     34 KC705 (Xilinx)
     35 
     36 - Kintex-7 XC7K325T FPGA
     37 - 1GB DDR3 memory
     38 - 128MB Linear BPI Flash
     39 
     40 
     41 Setting up the Board
     42 --------------------
     43 
     44 The serial port defaults to 115200 baud, no parity and 1 stop bit.
     45 A terminal emulator must be set accordingly to see the U-Boot prompt.
     46 
     47 
     48 Board Configurations LX60/LX110/LX200/ML605/KC705
     49 -------------------------------------------------
     50 
     51 The LX60/LX110/LX200/ML605 contain an 8-way DIP switch that controls
     52 the boot mapping and selects from a range of default ethernet MAC
     53 addresses.
     54 
     55 Boot Mapping (DIP switch 8):
     56 
     57     DIP switch 8 maps the system ROM address space (in which the
     58     reset vector resides) to either SRAM (off, 0, down) or Flash
     59     (on, 1, up).  This mapping is implemented in the FPGA bitstream
     60     and cannot be disabled by software, therefore DIP switch 8 is no
     61     available for application use. Note DIP switch 7 is reserved by
     62     Tensilica for future possible hardware use.
     63 
     64     Mapping to SRAM allows U-Boot to be debugged with an OCD/JTAG
     65     tool such as the Xtensa OCD Daemon connected via a suppored probe.
     66     See the tools documentation for supported probes and how to
     67     connect them.  Be aware that the board has only 128 KB of SRAM,
     68     therefore U-Boot must fit within this space to debug an image
     69     intended for the Flash.  This issues is discussed in a separate
     70     section toward the end.
     71 
     72     Mapping to flash allows U-Boot to start on reset, provided it
     73     has been programmed into the first two 64 KB sectors of the Flash.
     74 
     75     The Flash is always mapped at a device (memory mapped I/O) address
     76     (the address is board specific and is expressed as CFG_FLASH_BASE).
     77     The device address is used by U-Boot to program the flash, and may
     78     be used to specify an application to run or U-Boot image to boot.
     79 
     80 Default MAC Address (DIP switches 1-6):
     81 
     82     When the board is first powered on, or after the environment has
     83     been reinitialized, the ethernet MAC address receives a default
     84     value whose least significant 6 bits come from DIP switches 1-6.
     85     The default is 00:50:C2:13:6F:xx where xx ranges from 0..3F
     86     according to the DIP switches, where "on"==1 and "off"==0, and
     87     switch 1 is the least-significant bit.
     88 
     89     After initial startup, the MAC address is stored in the U-Boot
     90     environment variable 'ethaddr'. The user may change this to any
     91     other address with the "setenv" comamnd. After the environment
     92     has been saved to Flash by the "saveenv" command, this will be
     93     used and the DIP switches no longer consulted. DIP swithes 1-6
     94     may then be used for application purposes.
     95 
     96 The KC705 board contains 4-way DIP switch, way 1 is the boot mapping
     97 switch and ways 2-4 control the low three bits of the MAC address.
     98 
     99 
    100 Limitation of SDRAM Size for OCD Debugging on the LX60
    101 ------------------------------------------------------
    102 
    103 The XT-AV60 board has only 128 KB of SDRAM that can be mapped
    104 to the system ROM address space for debugging a ROM image under
    105 OCD/JTAG. This limits the useful size of U-Boot to 128 KB (0x20000)
    106 or the first 2 sectors of the flash.
    107 
    108 This can pose a problem if all the sources are compiled with -O0
    109 for debugging. The code size is then too large, in which case it
    110 would be necessary to temporarily alter the linker script to place
    111 the load addresses (LMA) in the RAM (VMA) so that OCD loads U-Boot
    112 directly there and does not unpack. In practice this is not really
    113 necessary as long as only a limited set of sources need to be
    114 debugged, because the image can still fit into the 128 KB SRAM.
    115 
    116 The recommended procedure for debugging is to first build U-Boot
    117 with the default optimization level (-Os), and then touch and
    118 rebuild incrementally with -O0 so that only the touched sources
    119 are recompiled with -O0. To build with -O0, pass it in the KCFLAGS
    120 variable to make.
    121 
    122 Because this problem is easy to fall into and difficult to debug
    123 if one doesn't expect it, the linker script provides a link-time
    124 check and fatal error message if the image size exceeds 128 KB.
    125 
    126