1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2010-2017 CS Systemes d'Information 4 * Florent Trinh Thai <florent.trinh-thai (at) c-s.fr> 5 * Christophe Leroy <christophe.leroy (at) c-s.fr> 6 * 7 * Board specific routines for the MCR3000 board 8 */ 9 10 #include <common.h> 11 #include <hwconfig.h> 12 #include <mpc8xx.h> 13 #include <fdt_support.h> 14 #include <asm/io.h> 15 16 DECLARE_GLOBAL_DATA_PTR; 17 18 #define SDRAM_MAX_SIZE (32 * 1024 * 1024) 19 20 static const uint cs1_dram_table_66[] = { 21 /* DRAM - single read. (offset 0 in upm RAM) */ 22 0x0F3DFC04, 0x0FEFBC04, 0x00BE7804, 0x0FFDF400, 23 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 24 25 /* DRAM - burst read. (offset 8 in upm RAM) */ 26 0x0F3DFC04, 0x0FEFBC04, 0x00BF7C04, 0x00FFFC00, 27 0x00FFFC00, 0x00FEF800, 0x0FFDF400, 0x1FFFFC05, 28 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 29 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 30 31 /* DRAM - single write. (offset 18 in upm RAM) */ 32 0x0F3DFC04, 0x0FEFB800, 0x00BF7404, 0x0FFEF804, 33 0x0FFDF404, 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 34 35 /* DRAM - burst write. (offset 20 in upm RAM) */ 36 0x0F3DFC04, 0x0FEFB800, 0x00BF7400, 0x00FFFC00, 37 0x00FFFC00, 0x00FFFC04, 0x0FFEF804, 0x0FFDF404, 38 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 39 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 40 41 /* refresh (offset 30 in upm RAM) */ 42 0x0FFDF404, 0x0FFEBC04, 0x0FFD7C84, 0x0FFFFC04, 43 0x0FFFFC04, 0x0FFFFC04, 0x1FFFFC85, 0xFFFFFFFF, 44 45 /* init */ 46 0x0FEEB874, 0x0FBD7474, 0x1FFFFC45, 0xFFFFFFFF, 47 48 /* exception. (offset 3c in upm RAM) */ 49 0xFFFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 50 }; 51 52 int ft_board_setup(void *blob, bd_t *bd) 53 { 54 const char *sync = "receive"; 55 56 ft_cpu_setup(blob, bd); 57 58 /* BRG */ 59 do_fixup_by_path_u32(blob, "/soc/cpm", "brg-frequency", 60 bd->bi_busfreq, 1); 61 62 /* MAC addr */ 63 fdt_fixup_ethernet(blob); 64 65 /* Bus Frequency for CPM */ 66 do_fixup_by_path_u32(blob, "/soc", "bus-frequency", bd->bi_busfreq, 1); 67 68 /* E1 interface - Set data rate */ 69 do_fixup_by_path_u32(blob, "/localbus/e1-wan", "data-rate", 2, 1); 70 71 /* E1 interface - Set channel phase to 0 */ 72 do_fixup_by_path_u32(blob, "/localbus/e1-wan", "channel-phase", 0, 1); 73 74 /* E1 interface - rising edge sync pulse transmit */ 75 do_fixup_by_path(blob, "/localbus/e1-wan", "rising-edge-sync-pulse", 76 sync, strlen(sync), 1); 77 78 return 0; 79 } 80 81 int checkboard(void) 82 { 83 serial_puts("BOARD: MCR3000 CSSI\n"); 84 85 return 0; 86 } 87 88 int dram_init(void) 89 { 90 immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR; 91 memctl8xx_t __iomem *memctl = &immap->im_memctl; 92 93 printf("UPMA init for SDRAM (CAS latency 2), "); 94 printf("init address 0x%08x, size ", (int)dram_init); 95 /* Configure UPMA for cs1 */ 96 upmconfig(UPMA, (uint *)cs1_dram_table_66, 97 sizeof(cs1_dram_table_66) / sizeof(uint)); 98 udelay(10); 99 out_be16(&memctl->memc_mptpr, 0x0200); 100 out_be32(&memctl->memc_mamr, 0x14904000); 101 udelay(10); 102 out_be32(&memctl->memc_or1, CONFIG_SYS_OR1_PRELIM); 103 out_be32(&memctl->memc_br1, CONFIG_SYS_BR1_PRELIM); 104 udelay(10); 105 out_be32(&memctl->memc_mcr, 0x80002830); 106 out_be32(&memctl->memc_mar, 0x00000088); 107 out_be32(&memctl->memc_mcr, 0x80002038); 108 udelay(200); 109 110 gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 111 SDRAM_MAX_SIZE); 112 113 return 0; 114 } 115 116 int misc_init_r(void) 117 { 118 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR; 119 iop8xx_t __iomem *iop = &immr->im_ioport; 120 121 /* Set port C13 as GPIO (BTN_ACQ_AL) */ 122 clrbits_be16(&iop->iop_pcpar, 0x4); 123 clrbits_be16(&iop->iop_pcdir, 0x4); 124 125 /* if BTN_ACQ_AL is pressed then bootdelay is changed to 60 second */ 126 if ((in_be16(&iop->iop_pcdat) & 0x0004) == 0) 127 env_set("bootdelay", "60"); 128 129 return 0; 130 } 131 132 int board_early_init_f(void) 133 { 134 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR; 135 136 /* 137 * Erase FPGA(s) for reboot 138 */ 139 clrbits_be32(&immr->im_cpm.cp_pbdat, 0x00020000); /* PROGFPGA down */ 140 setbits_be32(&immr->im_cpm.cp_pbdir, 0x00020000); /* PROGFPGA output */ 141 udelay(1); /* Wait more than 300ns */ 142 setbits_be32(&immr->im_cpm.cp_pbdat, 0x00020000); /* PROGFPGA up */ 143 144 return 0; 145 } 146
