1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2009 Renesas Solutions Corp. 4 * Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro (at) renesas.com> 5 * 6 * board/espt/lowlevel_init.S 7 */ 8 9 #include <config.h> 10 #include <asm/processor.h> 11 #include <asm/macro.h> 12 13 .global lowlevel_init 14 15 .text 16 .align 2 17 18 lowlevel_init: 19 20 write32 WDTCSR_A, WDTCSR_D 21 22 write32 WDTST_A, WDTST_D 23 24 write32 WDTBST_A, WDTBST_D 25 26 write32 CCR_A, CCR_CACHE_ICI_D 27 28 write32 MMUCR_A, MMU_CONTROL_TI_D 29 30 write32 MSTPCR0_A, MSTPCR0_D 31 32 write32 MSTPCR1_A, MSTPCR1_D 33 34 write32 RAMCR_A, RAMCR_D 35 36 /* 37 * Setting infomation from 38 * original ESPT-GIGA bootloader register 39 */ 40 write32 MMSEL_A, MMSEL_D 41 42 /* dummy */ 43 mov.l @r1, r2 44 mov.l @r1, r2 45 synco 46 47 write32 BCR_A, BCR_D 48 49 write32 CS0BCR_A, CS0BCR_D 50 51 write32 CS0WCR_A, CS0WCR_D 52 53 /* 54 * DDR-SDRAM setting 55 */ 56 57 /* set DDR-SDRAM dummy read */ 58 write32 MMSEL_A, MMSEL_D 59 60 write32 MMSEL_A, CS0_A 61 62 /* set DDR-SDRAM bus/endian etc */ 63 write32 MIM_U_A, MIM_U_D 64 65 write32 MIM_L_A, MIM_L_D0 66 67 write32 SDR_L_A, SDR_L_A_D0 68 69 write32 STR_L_A, STR_L_A_D0 70 71 /* DDR-SDRAM access control */ 72 write32 MIM_L_A, MIM_L_D1 73 74 write32 SCR_L_A, SCR_L_A_D0 75 76 write32 SCR_L_A, SCR_L_A_D1 77 78 write32 EMRS_A, EMRS_D 79 80 write32 MRS1_A, MRS1_D 81 82 write32 MIM_U_A, MIM_U_D 83 84 write32 MIM_L_A, MIM_L_A_D2 85 86 write32 SCR_L_A, SCR_L_A_D2 87 88 write32 SCR_L_A, SCR_L_A_D2 89 90 write32 MRS2_A, MRS2_D 91 92 /* wait 200us */ 93 wait_timer REPEAT_R3 94 95 /* GPIO setting */ 96 write16 PSEL0_A, PSEL0_D 97 98 write16 PSEL1_A, PSEL1_D 99 100 write16 PSEL2_A, PSEL2_D 101 102 write16 PSEL3_A, PSEL3_D 103 104 write16 PSEL4_A, PSEL4_D 105 106 write8 PADR_A, PADR_D 107 108 write16 PACR_A, PACR_D 109 110 write8 PBDR_A, PBDR_D 111 112 write16 PBCR_A, PBCR_D 113 114 write8 PCDR_A, PCDR_D 115 116 write16 PCCR_A, PCCR_D 117 118 write8 PDDR_A, PDDR_D 119 120 write16 PDCR_A, PDCR_D 121 122 write16 PECR_A, PECR_D 123 124 write16 PFCR_A, PFCR_D 125 126 write16 PGCR_A, PGCR_D 127 128 write16 PHCR_A, PHCR_D 129 130 write16 PICR_A, PICR_D 131 132 write8 PJDR_A, PJDR_D 133 134 write16 PJCR_A, PJCR_D 135 136 /* wait 50us */ 137 wait_timer REPEAT_R3 138 139 write8 PKDR_A, PKDR_D 140 141 write16 PKCR_A, PKCR_D 142 143 write16 PLCR_A, PLCR_D 144 145 write16 PMCR_A, PMCR_D 146 147 write16 PNCR_A, PNCR_D 148 149 write16 POCR_A, POCR_D 150 151 152 /* ICR0 ,ICR1 */ 153 write32 ICR0_A, ICR0_D 154 155 write32 ICR1_A, ICR1_D 156 157 /* USB Host */ 158 write32 USB_USBHSC_A, USB_USBHSC_D 159 160 write32 CCR_A, CCR_CACHE_D_2 161 162 rts 163 nop 164 165 .align 2 166 167 /* GPIO Crontrol Register */ 168 PACR_A: .long 0xFFEF0000 169 PBCR_A: .long 0xFFEF0002 170 PCCR_A: .long 0xFFEF0004 171 PDCR_A: .long 0xFFEF0006 172 PECR_A: .long 0xFFEF0008 173 PFCR_A: .long 0xFFEF000A 174 PGCR_A: .long 0xFFEF000C 175 PHCR_A: .long 0xFFEF000E 176 PICR_A: .long 0xFFEF0010 177 PJCR_A: .long 0xFFEF0012 178 PKCR_A: .long 0xFFEF0014 179 PLCR_A: .long 0xFFEF0016 180 PMCR_A: .long 0xFFEF0018 181 PNCR_A: .long 0xFFEF001A 182 POCR_A: .long 0xFFEF001C 183 184 /* GPIO Data Register */ 185 PADR_A: .long 0xFFEF0020 186 PBDR_A: .long 0xFFEF0022 187 PCDR_A: .long 0xFFEF0024 188 PDDR_A: .long 0xFFEF0026 189 PJDR_A: .long 0xFFEF0032 190 PKDR_A: .long 0xFFEF0034 191 192 /* GPIO Set data */ 193 PADR_D: .long 0x00000000 194 PACR_D: .word 0x1400 195 .align 2 196 PBDR_D: .long 0x00000000 197 PBCR_D: .word 0x555A 198 .align 2 199 PCDR_D: .long 0x00000000 200 PCCR_D: .word 0x5555 201 .align 2 202 PDDR_D: .long 0x00000000 203 PDCR_D: .word 0x0155 204 PECR_D: .word 0x0000 205 PFCR_D: .word 0x0000 206 PGCR_D: .word 0x0000 207 PHCR_D: .word 0x0000 208 PICR_D: .word 0x0800 209 PJDR_D: .long 0x00000006 210 PJCR_D: .word 0x5A57 211 .align 2 212 PKDR_D: .long 0x00000000 213 PKCR_D: .word 0xFFF9 214 .align 2 215 PLCR_D: .word 0xC330 216 PMCR_D: .word 0xFFFF 217 PNCR_D: .word 0x0242 218 POCR_D: .word 0x0000 219 220 /* Pin Select */ 221 PSEL0_A: .long 0xFFEF0070 222 PSEL1_A: .long 0xFFEF0072 223 PSEL2_A: .long 0xFFEF0074 224 PSEL3_A: .long 0xFFEF0076 225 PSEL4_A: .long 0xFFEF0078 226 PSEL0_D: .word 0x0001 227 PSEL1_D: .word 0x2400 228 PSEL2_D: .word 0x0000 229 PSEL3_D: .word 0x2421 230 PSEL4_D: .word 0x0000 231 .align 2 232 233 MMSEL_A: .long 0xFE600020 234 BCR_A: .long 0xFF801000 235 CS0BCR_A: .long 0xFF802000 236 CS0WCR_A: .long 0xFF802008 237 ICR0_A: .long 0xFFD00000 238 ICR1_A: .long 0xFFD0001C 239 240 MMSEL_D: .long 0xA5A50000 241 BCR_D: .long 0x05000000 242 CS0BCR_D: .long 0x232306F0 243 CS0WCR_D: .long 0x00011104 244 ICR0_D: .long 0x80C00000 245 ICR1_D: .long 0x00020000 246 247 /* RWBT Address */ 248 WDTST_A: .long 0xFFCC0000 249 WDTCSR_A: .long 0xFFCC0004 250 WDTBST_A: .long 0xFFCC0008 251 /* RWBT Data */ 252 WDTST_D: .long 0x5A000FFF 253 WDTCSR_D: .long 0xA5000000 254 WDTBST_D: .long 0x55000000 255 256 /* Cache Address */ 257 CCR_A: .long 0xFF00001C 258 MMUCR_A: .long 0xFF000010 259 RAMCR_A: .long 0xFF000074 260 261 /* Cache Data */ 262 CCR_CACHE_ICI_D:.long 0x00000800 263 CCR_CACHE_D_2: .long 0x00000103 264 MMU_CONTROL_TI_D:.long 0x00000004 265 RAMCR_D: .long 0x00000200 266 267 /* Low power mode control Address */ 268 MSTPCR0_A: .long 0xFFC80030 269 MSTPCR1_A: .long 0xFFC80038 270 /* Low power mode control Data */ 271 MSTPCR0_D: .long 0x00000000 272 MSTPCR1_D: .long 0x00000000 273 274 REPEAT0_R3: .long 0x00002000 275 REPEAT_R3: .long 0x00000200 276 CS0_A: .long 0xA8000000 277 278 MIM_U_A: .long 0xFE800008 279 MIM_L_A: .long 0xFE80000C 280 SCR_U_A: .long 0xFE800010 281 SCR_L_A: .long 0xFE800014 282 STR_U_A: .long 0xFE800018 283 STR_L_A: .long 0xFE80001C 284 SDR_U_A: .long 0xFE800030 285 SDR_L_A: .long 0xFE800034 286 EMRS_A: .long 0xFE902000 287 MRS1_A: .long 0xFE900B08 288 MRS2_A: .long 0xFE900308 289 290 MIM_U_D: .long 0x00000000 291 MIM_L_D0: .long 0x04100008 292 MIM_L_D1: .long 0x02EE0009 293 MIM_L_D2: .long 0x02EE0209 294 295 SDR_L_A_D0: .long 0x00000300 296 STR_L_A_D0: .long 0x00010040 297 MIM_L_A_D1: .long 0x04100009 298 SCR_L_A_D0: .long 0x00000003 299 SCR_L_A_D1: .long 0x00000002 300 MIM_L_A_D2: .long 0x04100209 301 SCR_L_A_D2: .long 0x00000004 302 303 SCR_L_NORMAL: .long 0x00000000 304 SCR_L_NOP: .long 0x00000001 305 SCR_L_PALL: .long 0x00000002 306 SCR_L_CKE_EN: .long 0x00000003 307 SCR_L_CBR: .long 0x00000004 308 309 STR_L_D: .long 0x000F3980 310 SDR_L_D: .long 0x00000400 311 EMRS_D: .long 0x00000000 312 MRS1_D: .long 0x00000000 313 MRS2_D: .long 0x00000000 314 315 /* USB */ 316 USB_USBHSC_A: .long 0xFFEC80F0 317 USB_USBHSC_D: .long 0x00000000 318
