| Up to higher level directory | |||
| Name | Date | Size | |
|---|---|---|---|
| bsc9132qds.c | 22-Oct-2020 | 9.3K | |
| ddr.c | 22-Oct-2020 | 5.4K | |
| Kconfig | 22-Oct-2020 | 195 | |
| law.c | 22-Oct-2020 | 844 | |
| MAINTAINERS | 22-Oct-2020 | 1K | |
| Makefile | 22-Oct-2020 | 288 | |
| README | 22-Oct-2020 | 5.1K | |
| spl_minimal.c | 22-Oct-2020 | 3.9K | |
| tlb.c | 22-Oct-2020 | 2.8K | |
README
1 Overview 2 -------- 3 The BSC9132 is a highly integrated device that targets the evolving 4 Microcell, Picocell, and Enterprise-Femto base station market subsegments. 5 6 The BSC9132 device combines Power Architecture e500 and DSP StarCore SC3850 7 core technologies with MAPLE-B2P baseband acceleration processing elements 8 to address the need for a high performance, low cost, integrated solution 9 that handles all required processing layers without the need for an 10 external device except for an RF transceiver or, in a Micro base station 11 configuration, a host device that handles the L3/L4 and handover between 12 sectors. 13 14 The BSC9132 SoC includes the following function and features: 15 - Power Architecture subsystem including two e500 processors with 16 512-Kbyte shared L2 cache 17 - Two StarCore SC3850 DSP subsystems, each with a 512-Kbyte private L2 18 cache 19 - 32 Kbyte of shared M3 memory 20 - The Multi Accelerator Platform Engine for Pico BaseStation Baseband 21 Processing (MAPLE-B2P) 22 - Two DDR3/3L memory interfaces with 32-bit data width (40 bits including 23 ECC), up to 1333 MHz data rate 24 - Dedicated security engine featuring trusted boot 25 - Two DMA controllers 26 - OCNDMA with four bidirectional channels 27 - SysDMA with sixteen bidirectional channels 28 - Interfaces 29 - Four-lane SerDes PHY 30 - PCI Express controller complies with the PEX Specification-Rev 2.0 31 - Two Common Public Radio Interface (CPRI) controller lanes 32 - High-speed USB 2.0 host and device controller with ULPI interface 33 - Enhanced secure digital (SD/MMC) host controller (eSDHC) 34 - Antenna interface controller (AIC), supporting four industry 35 standard JESD207/four custom ADI RF interfaces 36 - ADI lanes support both full duplex FDD support & half duplex TDD 37 - Universal Subscriber Identity Module (USIM) interface that 38 facilitates communication to SIM cards or Eurochip pre-paid phone 39 cards 40 - Two DUART, two eSPI, and two I2C controllers 41 - Integrated Flash memory controller (IFC) 42 - GPIO 43 - Sixteen 32-bit timers 44 45 The SC3850 core subsystem consists of the following: 46 - 32 KB, 8-way, level 1 instruction cache (L1 ICache) 47 - 32 KB, 8-way, level 1 data cache (L1 DCache) 48 - 512 KB, 8-way, level 2 unified instruction/data cache (L2 cache/M2 memory) 49 - Memory management unit (MMU) 50 - Global interrupt controller ( GIC) 51 - Debug and profiling unit (DPU) 52 - Two 32-bit quad timers 53 54 BSC9132QDS board Overview 55 ------------------------- 56 2Gbyte DDR3 (on board DDR), Dual Ranki 57 32Mbyte 16bit NOR flash 58 128Mbyte 2K page size NAND Flash 59 256 Kbit M24256 I2C EEPROM 60 128 Mbit SPI Flash memory 61 SD slot 62 USB-ULPI 63 eTSEC1: Connected to SGMII PHY 64 eTSEC2: Connected to SGMII PHY 65 PCIe 66 CPRI 67 SerDes 68 I2C RTC 69 DUART interface: supports one UARTs up to 115200 bps for console display 70 71 Frequency Combinations Supported 72 -------------------------------- 73 Core MHz/CCB MHz/DDR(MT/s) 74 1. CPU0/CPU1/CCB/DDR: 1000MHz/1000MHz/500MHz/800MHz 75 (SYSCLK = 100MHz, DDRCLK = 100MHz) 76 2. CPU0/CPU1/CCB/DDR: 1200MHz/1200MHz/600MHz/1330MHz 77 (SYSCLK = 100MHz, DDRCLK = 133MHz) 78 79 Boot Methods Supported 80 ----------------------- 81 1. NOR Flash 82 2. NAND Flash 83 3. SD Card 84 4. SPI flash 85 86 Default Boot Method 87 -------------------- 88 NOR boot 89 90 Building U-Boot 91 -------------- 92 To build the U-Boot for BSC9132QDS: 93 1. NOR Flash 94 make BSC9132QDS_NOR_DDRCLK100 : For 100MHZ DDR CLK 95 make BSC9132QDS_NOR_DDRCLK133 : For 133MHZ DDR CLK 96 2. NAND Flash : It is currently not supported 97 3. SPI Flash 98 make BSC9132QDS_SPIFLASH_DDRCLK100 : For 100MHZ DDR CLK 99 make BSC9132QDS_SPIFLASH_DDRCLK133 : For 133MHZ DDR CLK 100 4. SD Card 101 make BSC9132QDS_SDCARD_DDRCLK100 : For 100MHZ DDR CLK 102 make BSC9132QDS_SDCARD_DDRCLK133 : For 133MHZ DDR CLK 103 104 Memory map 105 ----------- 106 0x0000_0000 0x7FFF_FFFF DDR 2G cacheable 107 0x8000_0000 0x8FFF_FFFF NOR Flash 256M 108 0x9000_0000 0x9FFF_FFFF PCIe Memory 256M 109 0xA000_0000 0xA7FF_FFFF DSP core1 L2 space 128M 110 0xB000_0000 0xB0FF_FFFF DSP core0 M2 space 16M 111 0xB100_0000 0xB1FF_FFFF DSP core1 M2 space 16M 112 0xC000_0000 0xC000_7FFF M3 Memory 32K 113 0xC001_0000 0xC001_FFFF PCI Express I/O 64K 114 0xC100_0000 0xC13F_FFFF MAPLE-2F 4M 115 0xC1F0_0000 0xC1F7_FFFF PA SRAM Region 0 512K 116 0xC1F8_0000 0xC1FB_FFFF PA SRAM Region 1 512K 117 0xFED0_0000 0xFED0_3FFF SEC Secured RAM 16K 118 0xFEE0_0000 0xFEE0_0FFF DSP Boot ROM 4K 119 0xFF60_0000 0xFF6F_FFFF DSP CCSR 1M 120 0xFF70_0000 0xFF7F_FFFF PA CCSR 1M 121 0xFF80_0000 0xFFFF_FFFF Boot Page & NAND Buffer 8M 122 123 Flashing Images 124 --------------- 125 To place a new U-Boot image in the NAND flash and then boot 126 with that new image temporarily, use this: 127 tftp 1000000 u-boot-nand.bin 128 nand erase 0 100000 129 nand write 1000000 0 100000 130 reset 131 132 Using the Device Tree Source File 133 --------------------------------- 134 To create the DTB (Device Tree Binary) image file, 135 use a command similar to this: 136 137 dtc -b 0 -f -I dts -O dtb bsc9132qds.dts > bsc9132qds.dtb 138 139 Likely, that .dts file will come from here; 140 141 linux-2.6/arch/powerpc/boot/dts/bsc9132qds.dts 142 143 Booting Linux 144 ------------- 145 Place a linux uImage in the TFTP disk area. 146 147 tftp 1000000 uImage 148 tftp 2000000 rootfs.ext2.gz.uboot 149 tftp c00000 bsc9132qds.dtb 150 bootm 1000000 2000000 c00000 151
