1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2016 Freescale Semiconductor, Inc. 4 */ 5 6 #include <common.h> 7 #include <i2c.h> 8 #include <fdt_support.h> 9 #include <asm/io.h> 10 #include <asm/arch/clock.h> 11 #include <asm/arch/fsl_serdes.h> 12 #include <asm/arch/ppa.h> 13 #include <asm/arch/soc.h> 14 #include <hwconfig.h> 15 #include <ahci.h> 16 #include <mmc.h> 17 #include <scsi.h> 18 #include <fm_eth.h> 19 #include <fsl_csu.h> 20 #include <fsl_esdhc.h> 21 #include <power/mc34vr500_pmic.h> 22 #include "cpld.h" 23 #include <fsl_sec.h> 24 25 DECLARE_GLOBAL_DATA_PTR; 26 27 int board_early_init_f(void) 28 { 29 fsl_lsch2_early_init_f(); 30 31 return 0; 32 } 33 34 #ifndef CONFIG_SPL_BUILD 35 int checkboard(void) 36 { 37 static const char *freq[2] = {"100.00MHZ", "156.25MHZ"}; 38 u8 cfg_rcw_src1, cfg_rcw_src2; 39 u16 cfg_rcw_src; 40 u8 sd1refclk_sel; 41 42 puts("Board: LS1046ARDB, boot from "); 43 44 cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1); 45 cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2); 46 cpld_rev_bit(&cfg_rcw_src1); 47 cfg_rcw_src = cfg_rcw_src1; 48 cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2; 49 50 if (cfg_rcw_src == 0x44) 51 printf("QSPI vBank %d\n", CPLD_READ(vbank)); 52 else if (cfg_rcw_src == 0x40) 53 puts("SD\n"); 54 else 55 puts("Invalid setting of SW5\n"); 56 57 printf("CPLD: V%x.%x\nPCBA: V%x.0\n", CPLD_READ(cpld_ver), 58 CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver)); 59 60 puts("SERDES Reference Clocks:\n"); 61 sd1refclk_sel = CPLD_READ(sd1refclk_sel); 62 printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[sd1refclk_sel], freq[0]); 63 64 return 0; 65 } 66 67 int board_init(void) 68 { 69 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; 70 71 #ifdef CONFIG_SECURE_BOOT 72 /* 73 * In case of Secure Boot, the IBR configures the SMMU 74 * to allow only Secure transactions. 75 * SMMU must be reset in bypass mode. 76 * Set the ClientPD bit and Clear the USFCFG Bit 77 */ 78 u32 val; 79 val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); 80 out_le32(SMMU_SCR0, val); 81 val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); 82 out_le32(SMMU_NSCR0, val); 83 #endif 84 85 #ifdef CONFIG_FSL_CAAM 86 sec_init(); 87 #endif 88 89 #ifdef CONFIG_FSL_LS_PPA 90 ppa_init(); 91 #endif 92 93 /* invert AQR105 IRQ pins polarity */ 94 out_be32(&scfg->intpcr, AQR105_IRQ_MASK); 95 96 return 0; 97 } 98 99 int board_setup_core_volt(u32 vdd) 100 { 101 bool en_0v9; 102 103 en_0v9 = (vdd == 900) ? true : false; 104 cpld_select_core_volt(en_0v9); 105 106 return 0; 107 } 108 109 int get_serdes_volt(void) 110 { 111 return mc34vr500_get_sw_volt(SW4); 112 } 113 114 int set_serdes_volt(int svdd) 115 { 116 return mc34vr500_set_sw_volt(SW4, svdd); 117 } 118 119 int power_init_board(void) 120 { 121 int ret; 122 123 ret = power_mc34vr500_init(0); 124 if (ret) 125 return ret; 126 127 setup_chip_volt(); 128 129 return 0; 130 } 131 132 void config_board_mux(void) 133 { 134 #ifdef CONFIG_HAS_FSL_XHCI_USB 135 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; 136 u32 usb_pwrfault; 137 138 /* USB3 is not used, configure mux to IIC4_SCL/IIC4_SDA */ 139 out_be32(&scfg->rcwpmuxcr0, 0x3300); 140 out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1); 141 usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED << 142 SCFG_USBPWRFAULT_USB3_SHIFT) | 143 (SCFG_USBPWRFAULT_DEDICATED << 144 SCFG_USBPWRFAULT_USB2_SHIFT) | 145 (SCFG_USBPWRFAULT_SHARED << 146 SCFG_USBPWRFAULT_USB1_SHIFT); 147 out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault); 148 #endif 149 } 150 151 #ifdef CONFIG_MISC_INIT_R 152 int misc_init_r(void) 153 { 154 config_board_mux(); 155 return 0; 156 } 157 #endif 158 159 int ft_board_setup(void *blob, bd_t *bd) 160 { 161 u64 base[CONFIG_NR_DRAM_BANKS]; 162 u64 size[CONFIG_NR_DRAM_BANKS]; 163 164 /* fixup DT for the two DDR banks */ 165 base[0] = gd->bd->bi_dram[0].start; 166 size[0] = gd->bd->bi_dram[0].size; 167 base[1] = gd->bd->bi_dram[1].start; 168 size[1] = gd->bd->bi_dram[1].size; 169 170 fdt_fixup_memory_banks(blob, base, size, 2); 171 ft_cpu_setup(blob, bd); 172 173 #ifdef CONFIG_SYS_DPAA_FMAN 174 fdt_fixup_fman_ethernet(blob); 175 #endif 176 177 return 0; 178 } 179 #endif 180
