1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2014 Freescale Semiconductor, Inc. 4 */ 5 6 #ifndef __DDR_H__ 7 #define __DDR_H__ 8 struct board_specific_parameters { 9 u32 n_ranks; 10 u32 datarate_mhz_high; 11 u32 rank_gb; 12 u32 clk_adjust; 13 u32 wrlvl_start; 14 u32 wrlvl_ctl_2; 15 u32 wrlvl_ctl_3; 16 }; 17 18 /* 19 * These tables contain all valid speeds we want to override with board 20 * specific parameters. datarate_mhz_high values need to be in ascending order 21 * for each n_ranks group. 22 */ 23 24 static const struct board_specific_parameters udimm0[] = { 25 /* 26 * memory controller 0 27 * num| hi| rank| clk| wrlvl | wrlvl | wrlvl 28 * ranks| mhz| GB |adjst| start | ctl2 | ctl3 29 */ 30 {2, 2140, 0, 4, 4, 0x0, 0x0}, 31 {1, 2140, 0, 4, 4, 0x0, 0x0}, 32 {} 33 }; 34 35 /* DP-DDR DIMM */ 36 static const struct board_specific_parameters udimm2[] = { 37 /* 38 * memory controller 2 39 * num| hi| rank| clk| wrlvl | wrlvl | wrlvl 40 * ranks| mhz| GB |adjst| start | ctl2 | ctl3 41 */ 42 {2, 2140, 0, 4, 4, 0x0, 0x0}, 43 {1, 2140, 0, 4, 4, 0x0, 0x0}, 44 {} 45 }; 46 47 static const struct board_specific_parameters rdimm0[] = { 48 /* 49 * memory controller 0 50 * num| hi| rank| clk| wrlvl | wrlvl | wrlvl 51 * ranks| mhz| GB |adjst| start | ctl2 | ctl3 52 */ 53 {4, 2140, 0, 5, 4, 0x0, 0x0}, 54 {2, 2140, 0, 5, 4, 0x0, 0x0}, 55 {1, 2140, 0, 4, 4, 0x0, 0x0}, 56 {} 57 }; 58 59 /* DP-DDR DIMM */ 60 static const struct board_specific_parameters rdimm2[] = { 61 /* 62 * memory controller 2 63 * num| hi| rank| clk| wrlvl | wrlvl | wrlvl 64 * ranks| mhz| GB |adjst| start | ctl2 | ctl3 65 */ 66 {4, 2140, 0, 5, 4, 0x0, 0x0}, 67 {2, 2140, 0, 5, 4, 0x0, 0x0}, 68 {1, 2140, 0, 4, 4, 0x0, 0x0}, 69 {} 70 }; 71 72 static const struct board_specific_parameters *udimms[] = { 73 udimm0, 74 udimm0, 75 udimm2, 76 }; 77 78 static const struct board_specific_parameters *rdimms[] = { 79 rdimm0, 80 rdimm0, 81 rdimm2, 82 }; 83 84 85 #endif 86
