1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2015 Freescale Semiconductor, Inc. 4 */ 5 6 #ifndef __DDR_H__ 7 #define __DDR_H__ 8 struct board_specific_parameters { 9 u32 n_ranks; 10 u32 datarate_mhz_high; 11 u32 rank_gb; 12 u32 clk_adjust; 13 u32 wrlvl_start; 14 u32 wrlvl_ctl_2; 15 u32 wrlvl_ctl_3; 16 }; 17 18 /* 19 * These tables contain all valid speeds we want to override with board 20 * specific parameters. datarate_mhz_high values need to be in ascending order 21 * for each n_ranks group. 22 */ 23 24 static const struct board_specific_parameters udimm0[] = { 25 /* 26 * memory controller 0 27 * num| hi| rank| clk| wrlvl | wrlvl | wrlvl 28 * ranks| mhz| GB |adjst| start | ctl2 | ctl3 29 */ 30 {2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,}, 31 {2, 1666, 0, 10, 9, 0x090A0B0E, 0x0F11110C,}, 32 {2, 1900, 0, 12, 0xA, 0x0B0C0E11, 0x1214140F,}, 33 {2, 2300, 0, 12, 0xB, 0x0C0D0F12, 0x14161610,}, 34 {} 35 }; 36 37 /* DP-DDR DIMM */ 38 static const struct board_specific_parameters udimm2[] = { 39 /* 40 * memory controller 2 41 * num| hi| rank| clk| wrlvl | wrlvl | wrlvl 42 * ranks| mhz| GB |adjst| start | ctl2 | ctl3 43 */ 44 {2, 1350, 0, 8, 0xd, 0x0C0A0A00, 0x00000009,}, 45 {2, 1666, 0, 8, 0xd, 0x0C0A0A00, 0x00000009,}, 46 {2, 1900, 0, 8, 0xe, 0x0D0C0B00, 0x0000000A,}, 47 {2, 2200, 0, 8, 0xe, 0x0D0C0B00, 0x0000000A,}, 48 {} 49 }; 50 51 static const struct board_specific_parameters rdimm0[] = { 52 /* 53 * memory controller 0 54 * num| hi| rank| clk| wrlvl | wrlvl | wrlvl 55 * ranks| mhz| GB |adjst| start | ctl2 | ctl3 56 */ 57 {2, 1666, 0, 8, 0x0F, 0x0D0C0A09, 0x0B0C0E08,}, 58 {2, 1900, 0, 8, 0x10, 0x0F0D0B0A, 0x0B0E0F09,}, 59 {2, 2200, 0, 8, 0x13, 0x120F0E0B, 0x0D10110B,}, 60 {} 61 }; 62 63 static const struct board_specific_parameters *udimms[] = { 64 udimm0, 65 udimm0, 66 udimm2, 67 }; 68 69 static const struct board_specific_parameters *rdimms[] = { 70 rdimm0, 71 rdimm0, 72 udimm2, /* DP-DDR doesn't support RDIMM */ 73 }; 74 75 76 #endif 77
