1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2010-2012 Freescale Semiconductor, Inc. 4 * TsiChung Liew (Tsi-Chung.Liew (at) freescale.com) 5 */ 6 7 #include <common.h> 8 #include <spi.h> 9 #include <asm/io.h> 10 #include <asm/immap.h> 11 #include <mmc.h> 12 #include <fsl_esdhc.h> 13 14 DECLARE_GLOBAL_DATA_PTR; 15 16 int checkboard(void) 17 { 18 /* 19 * need to to: 20 * Check serial flash size. if 2mb evb, else 8mb demo 21 */ 22 puts("Board: "); 23 puts("Freescale MCF54418 Tower System\n"); 24 return 0; 25 }; 26 27 int dram_init(void) 28 { 29 u32 dramsize; 30 31 #if defined(CONFIG_SERIAL_BOOT) 32 /* 33 * Serial Boot: The dram is already initialized in start.S 34 * only require to return DRAM size 35 */ 36 dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000; 37 #else 38 sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM); 39 ccm_t *ccm = (ccm_t *)MMAP_CCM; 40 gpio_t *gpio = (gpio_t *) MMAP_GPIO; 41 pm_t *pm = (pm_t *) MMAP_PM; 42 u32 i; 43 44 dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000; 45 46 for (i = 0x13; i < 0x20; i++) { 47 if (dramsize == (1 << i)) 48 break; 49 } 50 51 out_8(&pm->pmcr0, 0x2E); 52 out_8(&gpio->mscr_sdram, 1); 53 54 clrbits_be16(&ccm->misccr2, CCM_MISCCR2_FBHALF); 55 setbits_be16(&ccm->misccr2, CCM_MISCCR2_DDR2CLK); 56 57 out_be32(&sdram->rcrcr, 0x40000000); 58 out_be32(&sdram->padcr, 0x01030203); 59 60 out_be32(&sdram->cr00, 0x01010101); 61 out_be32(&sdram->cr01, 0x00000101); 62 out_be32(&sdram->cr02, 0x01010100); 63 out_be32(&sdram->cr03, 0x01010000); 64 out_be32(&sdram->cr04, 0x00010101); 65 out_be32(&sdram->cr06, 0x00010100); 66 out_be32(&sdram->cr07, 0x00000001); 67 out_be32(&sdram->cr08, 0x01000001); 68 out_be32(&sdram->cr09, 0x00000100); 69 out_be32(&sdram->cr10, 0x00010001); 70 out_be32(&sdram->cr11, 0x00000200); 71 out_be32(&sdram->cr12, 0x01000002); 72 out_be32(&sdram->cr13, 0x00000000); 73 out_be32(&sdram->cr14, 0x00000100); 74 out_be32(&sdram->cr15, 0x02000100); 75 out_be32(&sdram->cr16, 0x02000407); 76 out_be32(&sdram->cr17, 0x02030007); 77 out_be32(&sdram->cr18, 0x02000100); 78 out_be32(&sdram->cr19, 0x0A030203); 79 out_be32(&sdram->cr20, 0x00020708); 80 out_be32(&sdram->cr21, 0x00050008); 81 out_be32(&sdram->cr22, 0x04030002); 82 out_be32(&sdram->cr23, 0x00000004); 83 out_be32(&sdram->cr24, 0x020A0000); 84 out_be32(&sdram->cr25, 0x0C00000E); 85 out_be32(&sdram->cr26, 0x00002004); 86 out_be32(&sdram->cr28, 0x00100010); 87 out_be32(&sdram->cr29, 0x00100010); 88 out_be32(&sdram->cr31, 0x07990000); 89 out_be32(&sdram->cr40, 0x00000000); 90 out_be32(&sdram->cr41, 0x00C80064); 91 out_be32(&sdram->cr42, 0x44520002); 92 out_be32(&sdram->cr43, 0x00C80023); 93 out_be32(&sdram->cr45, 0x0000C350); 94 out_be32(&sdram->cr56, 0x04000000); 95 out_be32(&sdram->cr57, 0x03000304); 96 out_be32(&sdram->cr58, 0x40040000); 97 out_be32(&sdram->cr59, 0xC0004004); 98 out_be32(&sdram->cr60, 0x0642C000); 99 out_be32(&sdram->cr61, 0x00000642); 100 asm("tpf"); 101 102 out_be32(&sdram->cr09, 0x01000100); 103 104 udelay(100); 105 #endif 106 gd->ram_size = dramsize; 107 108 return 0; 109 }; 110 111 int testdram(void) 112 { 113 return 0; 114 } 115
