1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2000-2003 4 * Wolfgang Denk, DENX Software Engineering, wd (at) denx.de. 5 * 6 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. 7 * TsiChung Liew (Tsi-Chung.Liew (at) freescale.com) 8 */ 9 10 #include <common.h> 11 #include <pci.h> 12 #include <asm/immap.h> 13 #include <asm/io.h> 14 15 DECLARE_GLOBAL_DATA_PTR; 16 17 int checkboard(void) 18 { 19 puts("Board: "); 20 puts("Freescale M54455 EVB\n"); 21 return 0; 22 }; 23 24 int dram_init(void) 25 { 26 u32 dramsize; 27 #ifdef CONFIG_CF_SBF 28 /* 29 * Serial Boot: The dram is already initialized in start.S 30 * only require to return DRAM size 31 */ 32 dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000 >> 1; 33 #else 34 sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM); 35 gpio_t *gpio = (gpio_t *)(MMAP_GPIO); 36 u32 i; 37 38 dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000 >> 1; 39 40 for (i = 0x13; i < 0x20; i++) { 41 if (dramsize == (1 << i)) 42 break; 43 } 44 i--; 45 46 out_8(&gpio->mscr_sdram, CONFIG_SYS_SDRAM_DRV_STRENGTH); 47 48 out_be32(&sdram->sdcs0, CONFIG_SYS_SDRAM_BASE | i); 49 out_be32(&sdram->sdcs1, CONFIG_SYS_SDRAM_BASE1 | i); 50 51 out_be32(&sdram->sdcfg1, CONFIG_SYS_SDRAM_CFG1); 52 out_be32(&sdram->sdcfg2, CONFIG_SYS_SDRAM_CFG2); 53 54 /* Issue PALL */ 55 out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2); 56 57 /* Issue LEMR */ 58 out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_EMOD | 0x408); 59 out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE | 0x300); 60 61 udelay(500); 62 63 /* Issue PALL */ 64 out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2); 65 66 /* Perform two refresh cycles */ 67 out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4); 68 out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4); 69 70 out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE | 0x200); 71 72 out_be32(&sdram->sdcr, 73 (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00); 74 75 udelay(100); 76 #endif 77 gd->ram_size = dramsize << 1; 78 79 return 0; 80 }; 81 82 int testdram(void) 83 { 84 /* TODO: XXX XXX XXX */ 85 printf("DRAM test not implemented!\n"); 86 87 return (0); 88 } 89 90 #if defined(CONFIG_IDE) 91 #include <ata.h> 92 93 int ide_preinit(void) 94 { 95 gpio_t *gpio = (gpio_t *) MMAP_GPIO; 96 u32 tmp; 97 98 tmp = (in_8(&gpio->par_fec) & GPIO_PAR_FEC_FEC1_UNMASK) | 0x10; 99 setbits_8(&gpio->par_fec, tmp); 100 tmp = ((in_be16(&gpio->par_feci2c) & 0xf0ff) | 101 (GPIO_PAR_FECI2C_MDC1_ATA_DIOR | GPIO_PAR_FECI2C_MDIO1_ATA_DIOW)); 102 setbits_be16(&gpio->par_feci2c, tmp); 103 104 setbits_be16(&gpio->par_ata, 105 GPIO_PAR_ATA_BUFEN | GPIO_PAR_ATA_CS1 | GPIO_PAR_ATA_CS0 | 106 GPIO_PAR_ATA_DA2 | GPIO_PAR_ATA_DA1 | GPIO_PAR_ATA_DA0 | 107 GPIO_PAR_ATA_RESET_RESET | GPIO_PAR_ATA_DMARQ_DMARQ | 108 GPIO_PAR_ATA_IORDY_IORDY); 109 setbits_be16(&gpio->par_pci, 110 GPIO_PAR_PCI_GNT3_ATA_DMACK | GPIO_PAR_PCI_REQ3_ATA_INTRQ); 111 112 return (0); 113 } 114 115 void ide_set_reset(int idereset) 116 { 117 atac_t *ata = (atac_t *) MMAP_ATA; 118 long period; 119 /* t1, t2, t3, t4, t5, t6, t9, tRD, tA */ 120 int piotms[5][9] = { 121 {70, 165, 60, 30, 50, 5, 20, 0, 35}, /* PIO 0 */ 122 {50, 125, 45, 20, 35, 5, 15, 0, 35}, /* PIO 1 */ 123 {30, 100, 30, 15, 20, 5, 10, 0, 35}, /* PIO 2 */ 124 {30, 80, 30, 10, 20, 5, 10, 0, 35}, /* PIO 3 */ 125 {25, 70, 20, 10, 20, 5, 10, 0, 35} 126 }; /* PIO 4 */ 127 128 if (idereset) { 129 /* control reset */ 130 out_8(&ata->cr, 0); 131 udelay(10000); 132 } else { 133 #define CALC_TIMING(t) (t + period - 1) / period 134 period = 1000000000 / gd->bus_clk; /* period in ns */ 135 136 /*ata->ton = CALC_TIMING (180); */ 137 out_8(&ata->t1, CALC_TIMING(piotms[2][0])); 138 out_8(&ata->t2w, CALC_TIMING(piotms[2][1])); 139 out_8(&ata->t2r, CALC_TIMING(piotms[2][1])); 140 out_8(&ata->ta, CALC_TIMING(piotms[2][8])); 141 out_8(&ata->trd, CALC_TIMING(piotms[2][7])); 142 out_8(&ata->t4, CALC_TIMING(piotms[2][3])); 143 out_8(&ata->t9, CALC_TIMING(piotms[2][6])); 144 145 /* IORDY enable */ 146 out_8(&ata->cr, 0x40); 147 udelay(200000); 148 /* IORDY enable */ 149 setbits_8(&ata->cr, 0x01); 150 } 151 } 152 #endif 153 154 #if defined(CONFIG_PCI) 155 /* 156 * Initialize PCI devices, report devices found. 157 */ 158 static struct pci_controller hose; 159 extern void pci_mcf5445x_init(struct pci_controller *hose); 160 161 void pci_init_board(void) 162 { 163 pci_mcf5445x_init(&hose); 164 } 165 #endif /* CONFIG_PCI */ 166 167 #if defined(CONFIG_FLASH_CFI_LEGACY) 168 #include <flash.h> 169 ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info) 170 { 171 int sect[] = CONFIG_SYS_ATMEL_SECT; 172 int sectsz[] = CONFIG_SYS_ATMEL_SECTSZ; 173 int i, j, k; 174 175 if (base != CONFIG_SYS_ATMEL_BASE) 176 return 0; 177 178 info->flash_id = 0x01000000; 179 info->portwidth = 1; 180 info->chipwidth = 1; 181 info->buffer_size = 1; 182 info->erase_blk_tout = 16384; 183 info->write_tout = 2; 184 info->buffer_write_tout = 5; 185 info->vendor = 0xFFF0; /* CFI_CMDSET_AMD_LEGACY */ 186 info->cmd_reset = 0x00F0; 187 info->interface = FLASH_CFI_X8; 188 info->legacy_unlock = 0; 189 info->manufacturer_id = (u16) ATM_MANUFACT; 190 info->device_id = ATM_ID_LV040; 191 info->device_id2 = 0; 192 193 info->ext_addr = 0; 194 info->cfi_version = 0x3133; 195 info->cfi_offset = 0x0000; 196 info->addr_unlock1 = 0x00000555; 197 info->addr_unlock2 = 0x000002AA; 198 info->name = "CFI conformant"; 199 200 info->size = 0; 201 info->sector_count = CONFIG_SYS_ATMEL_TOTALSECT; 202 info->start[0] = base; 203 for (k = 0, i = 0; i < CONFIG_SYS_ATMEL_REGION; i++) { 204 info->size += sect[i] * sectsz[i]; 205 206 for (j = 0; j < sect[i]; j++, k++) { 207 info->start[k + 1] = info->start[k] + sectsz[i]; 208 info->protect[k] = 0; 209 } 210 } 211 212 return 1; 213 } 214 #endif /* CONFIG_SYS_FLASH_CFI */ 215
