1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2007 Freescale Semiconductor, Inc. 4 * 5 * Author: Scott Wood <scottwood (at) freescale.com> 6 * Dave Liu <daveliu (at) freescale.com> 7 */ 8 9 #include <common.h> 10 #include <hwconfig.h> 11 #include <i2c.h> 12 #include <linux/libfdt.h> 13 #include <fdt_support.h> 14 #include <pci.h> 15 #include <mpc83xx.h> 16 #include <netdev.h> 17 #include <asm/io.h> 18 #include <ns16550.h> 19 #include <nand.h> 20 21 DECLARE_GLOBAL_DATA_PTR; 22 23 int board_early_init_f(void) 24 { 25 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; 26 27 if (im->pmc.pmccr1 & PMCCR1_POWER_OFF) 28 gd->flags |= GD_FLG_SILENT; 29 30 return 0; 31 } 32 33 #ifndef CONFIG_NAND_SPL 34 35 static u8 read_board_info(void) 36 { 37 u8 val8; 38 i2c_set_bus_num(0); 39 40 if (i2c_read(CONFIG_SYS_I2C_PCF8574A_ADDR, 0, 0, &val8, 1) == 0) 41 return val8; 42 else 43 return 0; 44 } 45 46 int checkboard(void) 47 { 48 static const char * const rev_str[] = { 49 "0.0", 50 "0.1", 51 "1.0", 52 "1.1", 53 "<unknown>", 54 }; 55 u8 info; 56 int i; 57 58 info = read_board_info(); 59 i = (!info) ? 4: info & 0x03; 60 61 printf("Board: Freescale MPC8315ERDB Rev %s\n", rev_str[i]); 62 63 return 0; 64 } 65 66 static struct pci_region pci_regions[] = { 67 { 68 bus_start: CONFIG_SYS_PCI_MEM_BASE, 69 phys_start: CONFIG_SYS_PCI_MEM_PHYS, 70 size: CONFIG_SYS_PCI_MEM_SIZE, 71 flags: PCI_REGION_MEM | PCI_REGION_PREFETCH 72 }, 73 { 74 bus_start: CONFIG_SYS_PCI_MMIO_BASE, 75 phys_start: CONFIG_SYS_PCI_MMIO_PHYS, 76 size: CONFIG_SYS_PCI_MMIO_SIZE, 77 flags: PCI_REGION_MEM 78 }, 79 { 80 bus_start: CONFIG_SYS_PCI_IO_BASE, 81 phys_start: CONFIG_SYS_PCI_IO_PHYS, 82 size: CONFIG_SYS_PCI_IO_SIZE, 83 flags: PCI_REGION_IO 84 } 85 }; 86 87 static struct pci_region pcie_regions_0[] = { 88 { 89 .bus_start = CONFIG_SYS_PCIE1_MEM_BASE, 90 .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS, 91 .size = CONFIG_SYS_PCIE1_MEM_SIZE, 92 .flags = PCI_REGION_MEM, 93 }, 94 { 95 .bus_start = CONFIG_SYS_PCIE1_IO_BASE, 96 .phys_start = CONFIG_SYS_PCIE1_IO_PHYS, 97 .size = CONFIG_SYS_PCIE1_IO_SIZE, 98 .flags = PCI_REGION_IO, 99 }, 100 }; 101 102 static struct pci_region pcie_regions_1[] = { 103 { 104 .bus_start = CONFIG_SYS_PCIE2_MEM_BASE, 105 .phys_start = CONFIG_SYS_PCIE2_MEM_PHYS, 106 .size = CONFIG_SYS_PCIE2_MEM_SIZE, 107 .flags = PCI_REGION_MEM, 108 }, 109 { 110 .bus_start = CONFIG_SYS_PCIE2_IO_BASE, 111 .phys_start = CONFIG_SYS_PCIE2_IO_PHYS, 112 .size = CONFIG_SYS_PCIE2_IO_SIZE, 113 .flags = PCI_REGION_IO, 114 }, 115 }; 116 117 void pci_init_board(void) 118 { 119 volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; 120 volatile sysconf83xx_t *sysconf = &immr->sysconf; 121 volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; 122 volatile law83xx_t *pci_law = immr->sysconf.pcilaw; 123 volatile law83xx_t *pcie_law = sysconf->pcielaw; 124 struct pci_region *reg[] = { pci_regions }; 125 struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, }; 126 127 /* Enable all 3 PCI_CLK_OUTPUTs. */ 128 clk->occr |= 0xe0000000; 129 130 /* 131 * Configure PCI Local Access Windows 132 */ 133 pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR; 134 pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB; 135 136 pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR; 137 pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB; 138 139 mpc83xx_pci_init(1, reg); 140 141 /* Configure the clock for PCIE controller */ 142 clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM, 143 SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1); 144 145 /* Deassert the resets in the control register */ 146 out_be32(&sysconf->pecr1, 0xE0008000); 147 out_be32(&sysconf->pecr2, 0xE0008000); 148 udelay(2000); 149 150 /* Configure PCI Express Local Access Windows */ 151 out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR); 152 out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB); 153 154 out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR); 155 out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB); 156 157 mpc83xx_pcie_init(2, pcie_reg); 158 } 159 160 #if defined(CONFIG_OF_BOARD_SETUP) 161 void fdt_tsec1_fixup(void *fdt, bd_t *bd) 162 { 163 const char disabled[] = "disabled"; 164 const char *path; 165 int ret; 166 167 if (hwconfig_arg_cmp("board_type", "tsec1")) { 168 return; 169 } else if (!hwconfig_arg_cmp("board_type", "ulpi")) { 170 printf("NOTICE: No or unknown board_type hwconfig specified.\n" 171 " Assuming board with TSEC1.\n"); 172 return; 173 } 174 175 ret = fdt_path_offset(fdt, "/aliases"); 176 if (ret < 0) { 177 printf("WARNING: can't find /aliases node\n"); 178 return; 179 } 180 181 path = fdt_getprop(fdt, ret, "ethernet0", NULL); 182 if (!path) { 183 printf("WARNING: can't find ethernet0 alias\n"); 184 return; 185 } 186 187 do_fixup_by_path(fdt, path, "status", disabled, sizeof(disabled), 1); 188 } 189 190 int ft_board_setup(void *blob, bd_t *bd) 191 { 192 ft_cpu_setup(blob, bd); 193 #ifdef CONFIG_PCI 194 ft_pci_setup(blob, bd); 195 #endif 196 fsl_fdt_fixup_dr_usb(blob, bd); 197 fdt_tsec1_fixup(blob, bd); 198 199 return 0; 200 } 201 #endif 202 203 int board_eth_init(bd_t *bis) 204 { 205 cpu_eth_init(bis); /* Initialize TSECs first */ 206 return pci_eth_init(bis); 207 } 208 209 #else /* CONFIG_NAND_SPL */ 210 211 int checkboard(void) 212 { 213 puts("Board: Freescale MPC8315ERDB\n"); 214 return 0; 215 } 216 217 void board_init_f(ulong bootflag) 218 { 219 board_early_init_f(); 220 NS16550_init((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), 221 CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE); 222 puts("NAND boot... "); 223 timer_init(); 224 dram_init(); 225 relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000, (gd_t *)gd, 226 CONFIG_SYS_NAND_U_BOOT_RELOC); 227 } 228 229 void board_init_r(gd_t *gd, ulong dest_addr) 230 { 231 nand_boot(); 232 } 233 234 void putc(char c) 235 { 236 if (gd->flags & GD_FLG_SILENT) 237 return; 238 239 if (c == '\n') 240 NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), '\r'); 241 242 NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), c); 243 } 244 245 #endif /* CONFIG_NAND_SPL */ 246
