1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2009 Freescale Semiconductor, Inc. 4 */ 5 6 #include <common.h> 7 #include <asm/io.h> 8 9 #include "bcsr.h" 10 11 void enable_8569mds_flash_write(void) 12 { 13 setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 17), BCSR17_FLASH_nWP); 14 } 15 16 void disable_8569mds_flash_write(void) 17 { 18 clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 17), BCSR17_FLASH_nWP); 19 } 20 21 void enable_8569mds_qe_uec(void) 22 { 23 #if defined(CONFIG_SYS_UCC_RGMII_MODE) 24 setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7), 25 BCSR7_UCC1_GETH_EN | BCSR7_UCC1_RGMII_EN); 26 setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 8), 27 BCSR8_UCC2_GETH_EN | BCSR8_UCC2_RGMII_EN); 28 setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 9), 29 BCSR9_UCC3_GETH_EN | BCSR9_UCC3_RGMII_EN); 30 setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 10), 31 BCSR10_UCC4_GETH_EN | BCSR10_UCC4_RGMII_EN); 32 #elif defined(CONFIG_SYS_UCC_RMII_MODE) 33 /* Set UCC1-4 working at RMII mode */ 34 clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7), 35 BCSR7_UCC1_GETH_EN | BCSR7_UCC1_RGMII_EN); 36 clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 8), 37 BCSR8_UCC2_GETH_EN | BCSR8_UCC2_RGMII_EN); 38 clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 9), 39 BCSR9_UCC3_GETH_EN | BCSR9_UCC3_RGMII_EN); 40 clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 10), 41 BCSR10_UCC4_GETH_EN | BCSR10_UCC4_RGMII_EN); 42 setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 9), BCSR9_UCC3_RMII_EN); 43 #endif 44 } 45 46 void disable_8569mds_brd_eeprom_write_protect(void) 47 { 48 clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7), BCSR7_BRD_WRT_PROTECT); 49 } 50
