1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * 4 * (C) Copyright 2009 Magnus Lilja <lilja.magnus (at) gmail.com> 5 * 6 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer (at) pengutronix.de> 7 */ 8 9 10 #include <common.h> 11 #include <netdev.h> 12 #include <asm/arch/clock.h> 13 #include <asm/arch/imx-regs.h> 14 #include <asm/arch/sys_proto.h> 15 #include <watchdog.h> 16 #include <power/pmic.h> 17 #include <fsl_pmic.h> 18 #include <errno.h> 19 20 DECLARE_GLOBAL_DATA_PTR; 21 22 #ifdef CONFIG_SPL_BUILD 23 void board_init_f(ulong bootflag) 24 { 25 /* 26 * copy ourselves from where we are running to where we were 27 * linked at. Use ulong pointers as all addresses involved 28 * are 4-byte-aligned. 29 */ 30 ulong *start_ptr, *end_ptr, *link_ptr, *run_ptr, *dst; 31 asm volatile ("ldr %0, =_start" : "=r"(start_ptr)); 32 asm volatile ("ldr %0, =_end" : "=r"(end_ptr)); 33 asm volatile ("ldr %0, =board_init_f" : "=r"(link_ptr)); 34 asm volatile ("adr %0, board_init_f" : "=r"(run_ptr)); 35 for (dst = start_ptr; dst < end_ptr; dst++) 36 *dst = *(dst+(run_ptr-link_ptr)); 37 /* 38 * branch to nand_boot's link-time address. 39 */ 40 asm volatile("ldr pc, =nand_boot"); 41 } 42 #endif 43 44 int dram_init(void) 45 { 46 /* dram_init must store complete ramsize in gd->ram_size */ 47 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, 48 PHYS_SDRAM_1_SIZE); 49 return 0; 50 } 51 52 int board_early_init_f(void) 53 { 54 /* CS5: CPLD incl. network controller */ 55 static const struct mxc_weimcs cs5 = { 56 /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ 57 CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 24, 0, 4, 3), 58 /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ 59 CSCR_L(2, 2, 2, 5, 2, 0, 5, 2, 0, 0, 0, 1), 60 /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ 61 CSCR_A(2, 2, 2, 2, 0, 0, 2, 2, 0, 0, 0, 0, 0, 0) 62 }; 63 64 mxc_setup_weimcs(5, &cs5); 65 66 /* Setup UART1 and SPI2 pins */ 67 mx31_uart1_hw_init(); 68 mx31_spi2_hw_init(); 69 70 return 0; 71 } 72 73 int board_init(void) 74 { 75 /* adress of boot parameters */ 76 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; 77 78 return 0; 79 } 80 81 int board_late_init(void) 82 { 83 u32 val; 84 struct pmic *p; 85 int ret; 86 87 ret = pmic_init(CONFIG_FSL_PMIC_BUS); 88 if (ret) 89 return ret; 90 91 p = pmic_get("FSL_PMIC"); 92 if (!p) 93 return -ENODEV; 94 /* Enable RTC battery */ 95 pmic_reg_read(p, REG_POWER_CTL0, &val); 96 pmic_reg_write(p, REG_POWER_CTL0, val | COINCHEN); 97 pmic_reg_write(p, REG_INT_STATUS1, RTCRSTI); 98 #ifdef CONFIG_HW_WATCHDOG 99 hw_watchdog_init(); 100 #endif 101 return 0; 102 } 103 104 int checkboard(void) 105 { 106 printf("Board: MX31PDK\n"); 107 return 0; 108 } 109 110 int board_eth_init(bd_t *bis) 111 { 112 int rc = 0; 113 #ifdef CONFIG_SMC911X 114 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); 115 #endif 116 return rc; 117 } 118