1 Overview 2 ========= 3 The P2041 Processor combines four Power Architecture processor cores 4 with high-performance datapath acceleration architecture(DPAA), CoreNet 5 fabric infrastructure, as well as network and peripheral bus interfaces 6 required for networking, telecom/datacom, wireless infrastructure, and 7 military/aerospace applications. 8 9 P2041RDB board is a quad core platform supporting the P2041 processor 10 of QorIQ DPAA series. 11 12 Boot from NOR flash 13 =================== 14 1. Build image 15 make P2041RDB_config 16 make all 17 18 2. Program image 19 => tftp 1000000 u-boot.bin 20 => protect off all 21 => erase eff40000 efffffff 22 => cp.b 1000000 eff40000 c0000 23 24 3. Program RCW 25 => tftp 1000000 rcw.bin 26 => protect off all 27 => erase e8000000 e801ffff 28 => cp.b 1000000 e8000000 50 29 30 4. Program FMAN Firmware ucode 31 => tftp 1000000 ucode.bin 32 => protect off all 33 => erase eff00000 eff3ffff 34 => cp.b 1000000 eff00000 2000 35 36 5. Change DIP-switch 37 SW1[1-5] = 10110 38 Note: 1 stands for 'on', 0 stands for 'off' 39 40 Boot from SDCard 41 =================== 42 1. Build image 43 make P2041RDB_SDCARD_config 44 make all 45 46 2. Generate PBL imge 47 Use PE tool to produce a image used to be programed to 48 SDCard which contains RCW and U-Boot image. 49 50 3. Program the PBL image to SDCard 51 => tftp 1000000 pbl_sd.bin 52 => mmcinfo 53 => mmc write 1000000 8 672 54 55 4. Program FMAN Firmware ucode 56 => tftp 1000000 ucode.bin 57 => mmc write 1000000 690 10 58 59 5. Change DIP-switch 60 SW1[1-5] = 01100 61 Note: 1 stands for 'on', 0 stands for 'off' 62 63 Boot from SPI flash 64 =================== 65 1. Build image 66 make P2041RDB_SPIFLASH_config 67 make all 68 69 2. Generate PBL imge 70 Use PE tool to produce a image used to be programed to 71 SPI flash which contains RCW and U-Boot image. 72 73 3. Program the PBL image to SPI flash 74 => tftp 1000000 pbl_spi.bin 75 => spi probe 0 76 => sf erase 0 100000 77 => sf write 1000000 0 $filesize 78 79 4. Program FMAN Firmware ucode 80 => tftp 1000000 ucode.bin 81 => sf erase 110000 10000 82 => sf write 1000000 110000 $filesize 83 84 5. Change DIP-switch 85 SW1[1-5] = 10100 86 Note: 1 stands for 'on', 0 stands for 'off' 87 88 CPLD command 89 ============ 90 The CPLD is used to control the power sequence and some serdes lane 91 mux function. 92 93 cpld reset - hard reset to default bank 94 cpld reset altbank - reset to alternate bank 95 cpld lane_mux <lane> <mux_value> - set multiplexed lane pin 96 lane 6: 0 -> slot1 (Default) 97 1 -> SGMII 98 lane a: 0 -> slot2 (Default) 99 1 -> AURORA 100 lane c: 0 -> slot2 (Default) 101 1 -> SATA0 102 lane d: 0 -> slot2 (Default) 103 1 -> SATA1 104 105 Using the Device Tree Source File 106 ================================= 107 To create the DTB (Device Tree Binary) image file, use a command 108 similar to this: 109 dtc -O dtb -b 0 -p 1024 p2041rdb.dts > p2041rdb.dtb 110 111 Or use the following command: 112 {linux-2.6}/make p2041rdb.dtb ARCH=powerpc 113 114 then the dtb file will be generated under the following directory: 115 {linux-2.6}/arch/powerpc/boot/p2041rdb.dtb 116 117 Booting Linux 118 ============= 119 Place a linux uImage in the TFTP disk area. 120 tftp 1000000 uImage 121 tftp 2000000 rootfs.ext2.gz.uboot 122 tftp 3000000 p2041rdb.dtb 123 bootm 1000000 2000000 3000000 124
