1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2013 Freescale Semiconductor, Inc. 4 */ 5 6 #ifndef __T1040QDS_QIXIS_H__ 7 #define __T1040QDS_QIXIS_H__ 8 9 /* Definitions of QIXIS Registers for T1040QDS */ 10 11 /* BRDCFG4[4:7]] select EC1 and EC2 as a pair */ 12 #define BRDCFG4_EMISEL_MASK 0xE0 13 #define BRDCFG4_EMISEL_SHIFT 5 14 15 /* BRDCFG5[0:1] controls routing and use of I2C3 & I2C4 ports*/ 16 #define BRDCFG5_IMX_MASK 0xC0 17 #define BRDCFG5_IMX_DIU 0x80 18 19 /* BRDCFG9[2] controls EPHY2 Clock */ 20 #define BRDCFG9_EPHY2_MASK 0x20 21 #define BRDCFG9_EPHY2_VAL 0x00 22 23 /* BRDCFG15[3] controls LCD Panel Powerdown*/ 24 #define BRDCFG15_LCDPD_MASK 0x10 25 #define BRDCFG15_LCDPD_ENABLED 0x00 26 27 /* BRDCFG15[6:7] controls DIU MUX selction*/ 28 #define BRDCFG15_DIUSEL_MASK 0x03 29 #define BRDCFG15_DIUSEL_HDMI 0x00 30 31 /* SYSCLK */ 32 #define QIXIS_SYSCLK_66 0x0 33 #define QIXIS_SYSCLK_83 0x1 34 #define QIXIS_SYSCLK_100 0x2 35 #define QIXIS_SYSCLK_125 0x3 36 #define QIXIS_SYSCLK_133 0x4 37 #define QIXIS_SYSCLK_150 0x5 38 #define QIXIS_SYSCLK_160 0x6 39 #define QIXIS_SYSCLK_166 0x7 40 #define QIXIS_SYSCLK_64 0x8 41 42 /* DDRCLK */ 43 #define QIXIS_DDRCLK_66 0x0 44 #define QIXIS_DDRCLK_100 0x1 45 #define QIXIS_DDRCLK_125 0x2 46 #define QIXIS_DDRCLK_133 0x3 47 48 49 #define QIXIS_SRDS1CLK_122 0x5a 50 #define QIXIS_SRDS1CLK_125 0x5e 51 #endif 52
