1 Overview 2 -------- 3 The T1040RDB is a Freescale reference board that hosts the T1040 SoC 4 (and variants). Variants inclued T1042 presonality of T1040, in which 5 case T1040RDB can also be called T1042RDB. 6 7 The T1042RDB is a Freescale reference board that hosts the T1042 SoC 8 (and variants). The board is similar to T1040RDB, T1040 is a reduced 9 personality of T1040 SoC without Integrated 8-port Gigabit(L2 Switch). 10 11 The T1042RDB_PI is a Freescale reference board that hosts the T1042 SoC. 12 (a personality of T1040 SoC). The board is similar to T1040RDB but is 13 designed specially with low power features targeted for Printing Image Market. 14 15 The T1040D4RDB is a Freescale reference board that hosts the T1040 SoC. 16 The board is re-designed T1040RDB board with following changes : 17 - Support of DDR4 memory and some enhancements 18 19 The T1042D4RDB is a Freescale reference board that hosts the T1042 SoC. 20 The board is re-designed T1040RDB board with following changes : 21 - Support of DDR4 memory 22 - Support for 0x86 serdes protocol which can support following interfaces 23 - 2 RGMII's on DTSEC4, DTSEC5 24 - 3 SGMII on DTSEC1, DTSEC2 & DTSEC3 25 26 Basic difference's among T1040RDB, T1042RDB_PI, T1042RDB 27 ------------------------------------------------------------------------- 28 Board Si Protocol Targeted Market 29 ------------------------------------------------------------------------- 30 T1040RDB T1040 0x66 Networking 31 T1040RDB T1042 0x86 Networking 32 T1042RDB_PI T1042 0x06 Printing & Imaging 33 T1040D4RDB T1040 0x66 Networking 34 T1042D4RDB T1042 0x86 Networking 35 36 37 T1040 SoC Overview 38 ------------------ 39 The QorIQ T1040/T1042 processor support four integrated 64-bit e5500 PA 40 processor cores with high-performance data path acceleration architecture 41 and network peripheral interfaces required for networking & telecommunications. 42 43 The T1040/T1042 SoC includes the following function and features: 44 45 - Four e5500 cores, each with a private 256 KB L2 cache 46 - 256 KB shared L3 CoreNet platform cache (CPC) 47 - Interconnect CoreNet platform 48 - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving 49 support 50 - Data Path Acceleration Architecture (DPAA) incorporating acceleration 51 for the following functions: 52 - Packet parsing, classification, and distribution 53 - Queue management for scheduling, packet sequencing, and congestion 54 management 55 - Cryptography Acceleration (SEC 5.0) 56 - RegEx Pattern Matching Acceleration (PME 2.2) 57 - IEEE Std 1588 support 58 - Hardware buffer management for buffer allocation and deallocation 59 - Ethernet interfaces 60 - Integrated 8-port Gigabit Ethernet switch (T1040 only) 61 - Four 1 Gbps Ethernet controllers 62 - Two RGMII interfaces or one RGMII and one MII interfaces 63 - High speed peripheral interfaces 64 - Four PCI Express 2.0 controllers running at up to 5 GHz 65 - Two SATA controllers supporting 1.5 and 3.0 Gb/s operation 66 - Upto two QSGMII interface 67 - Upto six SGMII interface supporting 1000 Mbps 68 - One SGMII interface supporting upto 2500 Mbps 69 - Additional peripheral interfaces 70 - Two USB 2.0 controllers with integrated PHY 71 - SD/eSDHC/eMMC 72 - eSPI controller 73 - Four I2C controllers 74 - Four UARTs 75 - Four GPIO controllers 76 - Integrated flash controller (IFC) 77 - LCD and HDMI interface (DIU) with 12 bit dual data rate 78 - TDM interface 79 - Multicore programmable interrupt controller (PIC) 80 - Two 8-channel DMA engines 81 - Single source clocking implementation 82 - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB) 83 84 T1040 SoC Personalities 85 ------------------------- 86 T1022 Personality: 87 T1022 is a reduced personality of T1040 with less core/clusters. 88 89 T1042 Personality: 90 T1042 is a reduced personality of T1040 without Integrated 8-port Gigabit 91 Ethernet switch. Rest of the blocks are same as T1040 92 93 94 T1040RDB board Overview 95 ------------------------- 96 - SERDES Connections, 8 lanes information: 97 1: None 98 2: SGMII 99 3: QSGMII 100 4: QSGMII 101 5: PCIe1 x1 slot 102 6: mini PCIe connector 103 7: mini PCIe connector 104 8: SATA connector 105 - DDR Controller 106 - Supports rates of up to 1600 MHz data-rate 107 - Supports one DDR3LP UDIMM/RDIMMs, of single-, dual- or quad-rank types. 108 - IFC/Local Bus 109 - NAND flash: 1GB 8-bit NAND flash 110 - NOR: 128MB 16-bit NOR Flash 111 - Ethernet 112 - Two on-board RGMII 10/100/1G ethernet ports. 113 - CPLD 114 - Clocks 115 - System and DDR clock (SYSCLK, DDRCLK) 116 - SERDES clocks 117 - Power Supplies 118 - USB 119 - Supports two USB 2.0 ports with integrated PHYs 120 - Two type A ports with 5V (a] 1.5A per port. 121 - SDHC 122 - SDHC/SDXC connector 123 - SPI 124 - On-board 64MB SPI flash 125 - Other IO 126 - Two Serial ports 127 - Four I2C ports 128 129 T1042RDB_PI board Overview 130 ------------------------- 131 - SERDES Connections, 8 lanes information: 132 1, 2, 3, 4 : PCIe x4 slot 133 5: mini PCIe connector 134 6: mini PCIe connector 135 7: NA 136 8: SATA connector 137 - DDR Controller 138 - Supports rates of up to 1600 MHz data-rate 139 - Supports one DDR3LP UDIMM/RDIMMs, of single-, dual- or quad-rank types. 140 - IFC/Local Bus 141 - NAND flash: 1GB 8-bit NAND flash 142 - NOR: 128MB 16-bit NOR Flash 143 - Ethernet 144 - Two on-board RGMII 10/100/1G ethernet ports. 145 - CPLD 146 - Clocks 147 - System and DDR clock (SYSCLK, DDRCLK) 148 - SERDES clocks 149 - Video 150 - DIU supports video at up to 1280x1024x32bpp 151 - Power Supplies 152 - USB 153 - Supports two USB 2.0 ports with integrated PHYs 154 - Two type A ports with 5V (a] 1.5A per port. 155 - SDHC 156 - SDHC/SDXC connector 157 - SPI 158 - On-board 64MB SPI flash 159 - Other IO 160 - Two Serial ports 161 - Four I2C ports 162 163 Memory map 164 ----------- 165 The addresses in brackets are physical addresses. 166 167 Start Address End Address Description Size 168 0xF_FFDF_0000 0xF_FFDF_0FFF IFC - CPLD 4KB 169 0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB 170 0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB 171 0xF_F803_0000 0xF_F803_FFFF PCI Express 4 I/O Space 64KB 172 0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB 173 0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB 174 0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB 175 0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB 176 0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB 177 0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB 178 0xF_0000_0000 0xF_003F_FFFF DCSR 4MB 179 0xC_3000_0000 0xC_3FFF_FFFF PCI Express 4 Mem Space 256MB 180 0xC_2000_0000 0xC_2FFF_FFFF PCI Express 3 Mem Space 256MB 181 0xC_1000_0000 0xC_1FFF_FFFF PCI Express 2 Mem Space 256MB 182 0xC_0000_0000 0xC_0FFF_FFFF PCI Express 1 Mem Space 256MB 183 0x0_0000_0000 0x0_ffff_ffff DDR 2GB 184 185 186 NOR Flash memory Map 187 --------------------- 188 Start End Definition Size 189 0xEFF40000 0xEFFFFFFF U-Boot (current bank) 768KB 190 0xEFF20000 0xEFF3FFFF U-Boot env (current bank) 128KB 191 0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB 192 0xED300000 0xEFEFFFFF rootfs (alt bank) 44MB 193 0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB 194 0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB 195 0xEC000000 0xEC01FFFF RCW (alt bank) 128KB 196 0xEBF40000 0xEBFFFFFF U-Boot (alt bank) 768KB 197 0xEBF20000 0xEBF3FFFF U-Boot env (alt bank) 128KB 198 0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB 199 0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB 200 0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 11MB + 512KB 201 0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB 202 0xE8000000 0xE801FFFF RCW (current bank) 128KB 203 204 205 Various Software configurations/environment variables/commands 206 -------------------------------------------------------------- 207 The below commands apply to the board 208 209 1. U-Boot environment variable hwconfig 210 The default hwconfig is: 211 hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;usb1: 212 dr_mode=host,phy_type=utmi 213 Note: For USB gadget set "dr_mode=peripheral" 214 215 2. FMAN Ucode versions 216 fsl_fman_ucode_t1040.bin 217 218 3. Switching to alternate bank 219 Commands for switching to alternate bank. 220 221 1. To change from vbank0 to vbank4 222 => cpld reset altbank (it will boot using vbank4) 223 224 2.To change from vbank4 to vbank0 225 => cpld reset (it will boot using vbank0) 226 227 NAND boot with 2 Stage boot loader 228 ---------------------------------- 229 PBL initialise the internal SRAM and copy SPL(160KB) in SRAM. 230 SPL further initialise DDR using SPD and environment variables and copy 231 U-Boot(768 KB) from flash to DDR. 232 Finally SPL transer control to U-Boot for futher booting. 233 234 SPL has following features: 235 - Executes within 256K 236 - No relocation required 237 238 Run time view of SPL framework during boot :- 239 ----------------------------------------------- 240 Area | Address | 241 ----------------------------------------------- 242 Secure boot | 0xFFFC0000 (32KB) | 243 headers | | 244 ----------------------------------------------- 245 GD, BD | 0xFFFC8000 (4KB) | 246 ----------------------------------------------- 247 ENV | 0xFFFC9000 (8KB) | 248 ----------------------------------------------- 249 HEAP | 0xFFFCB000 (30KB) | 250 ----------------------------------------------- 251 STACK | 0xFFFD8000 (22KB) | 252 ----------------------------------------------- 253 U-Boot SPL | 0xFFFD8000 (160KB) | 254 ----------------------------------------------- 255 256 NAND Flash memory Map on T104xRDB 257 ------------------------------------------ 258 Start End Definition Size 259 0x000000 0x0FFFFF U-Boot 1MB 260 0x180000 0x19FFFF U-Boot env 128KB 261 0x280000 0x29FFFF FMAN Ucode 128KB 262 0x380000 0x39FFFF QE Firmware 128KB 263 264 SD Card memory Map on T104xRDB 265 ------------------------------------------ 266 Block #blocks Definition Size 267 0x008 2048 U-Boot 1MB 268 0x800 0024 U-Boot env 8KB 269 0x820 0256 FMAN Ucode 128KB 270 0x920 0256 QE Firmware 128KB 271 272 SPI Flash memory Map on T104xRDB 273 ------------------------------------------ 274 Start End Definition Size 275 0x000000 0x0FFFFF U-Boot 1MB 276 0x100000 0x101FFF U-Boot env 8KB 277 0x110000 0x12FFFF FMAN Ucode 128KB 278 0x130000 0x14FFFF QE Firmware 128KB 279 280 Please note QE Firmware is only valid for T1040RDB 281 282 283 Switch Settings for T104xRDB boards: (ON is 0, OFF is 1) 284 ========================================================== 285 NOR boot SW setting: 286 SW1: 00010011 287 SW2: 10111011 288 SW3: 11100001 289 290 NAND boot SW setting: 291 SW1: 10001000 292 SW2: 00111011 293 SW3: 11110001 294 295 SPI boot SW setting: 296 SW1: 00100010 297 SW2: 10111011 298 SW3: 11100001 299 300 SD boot SW setting: 301 SW1: 00100000 302 SW2: 00111011 303 SW3: 11100001 304 305 Switch Settings for T104xD4RDB boards: (ON is 0, OFF is 1) 306 ============================================================= 307 NOR boot SW setting: 308 SW1: 00010011 309 SW2: 10111001 310 SW3: 11100001 311 312 NAND boot SW setting: 313 SW1: 10001000 314 SW2: 00111001 315 SW3: 11110001 316 317 SPI boot SW setting: 318 SW1: 00100010 319 SW2: 10111001 320 SW3: 11100001 321 322 SD boot SW setting: 323 SW1: 00100000 324 SW2: 00111001 325 SW3: 11100001 326 327 PBL-based image generation 328 ========================== 329 Changes only the required register bit in in PBI commands. 330 331 Provides reference code which might needs some 332 modification as per requirement. 333 example: 334 By default PBI_SRC=14 (which is for IFC-NAND/NOR) in rcw.cfg file 335 which needs to be changed for SPI and SD. 336 337 For SD-boot 338 ============== 339 1. Set RCW[192:195], PBI_SRC bits as 6 in RCW file (t1040d4_rcw.cfg type files) 340 341 example: 342 RCW file: board/freescale/t104xrdb/t1040d4_rcw.cfg 343 344 Change 345 66000002 40000002 ec027000 01000000 346 to 347 66000002 40000002 6c027000 01000000 348 349 2. SD does not support flush so remove flush from pbl, make changes in 350 tools/pblimage.c file, Update value of pbl_end_cmd[0] = 0x09138000 351 with 0x091380c0 352 353 For SPI-boot 354 ============== 355 1. Set RCW[192:195], PBI_SRC bits as 5 in RCW file (t1040d4_rcw.cfg type files) 356 357 example: 358 RCW file: board/freescale/t104xrdb/t1040d4_rcw.cfg 359 360 Change 361 66000002 40000002 ec027000 01000000 362 to 363 66000002 40000002 5c027000 01000000 364 365 2. SPI does not support flush so remove flush from pbl, make changes in 366 tools/pblimage.c file, Update value of pbl_end_cmd[0] = 0x09138000 367 with 0x091380c0 368