1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2017 General Electric Company 4 * 5 * Based on board/freescale/mx53loco/mx53loco_video.c: 6 * 7 * Copyright (C) 2012 Freescale Semiconductor, Inc. 8 * Fabio Estevam <fabio.estevam (at) freescale.com> 9 */ 10 11 #include <common.h> 12 #include <linux/list.h> 13 #include <asm/gpio.h> 14 #include <asm/arch/iomux-mx53.h> 15 #include <linux/fb.h> 16 #include <ipu_pixfmt.h> 17 #include <asm/arch/crm_regs.h> 18 #include <asm/arch/imx-regs.h> 19 #include <asm/io.h> 20 #include <pwm.h> 21 #include "ppd_gpio.h" 22 23 #define MX53PPD_LCD_POWER IMX_GPIO_NR(3, 24) 24 25 static struct fb_videomode const nv_spwg = { 26 .name = "NV-SPWGRGB888", 27 .refresh = 60, 28 .xres = 800, 29 .yres = 480, 30 .pixclock = 15384, 31 .left_margin = 16, 32 .right_margin = 210, 33 .upper_margin = 10, 34 .lower_margin = 22, 35 .hsync_len = 30, 36 .vsync_len = 13, 37 .sync = FB_SYNC_EXT, 38 .vmode = FB_VMODE_NONINTERLACED 39 }; 40 41 void setup_iomux_lcd(void) 42 { 43 static const iomux_v3_cfg_t lcd_pads[] = { 44 MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK, 45 MX53_PAD_DI0_PIN15__IPU_DI0_PIN15, 46 MX53_PAD_DI0_PIN2__IPU_DI0_PIN2, 47 MX53_PAD_DI0_PIN3__IPU_DI0_PIN3, 48 MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0, 49 MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1, 50 MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2, 51 MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3, 52 MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4, 53 MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5, 54 MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6, 55 MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7, 56 MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8, 57 MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9, 58 MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10, 59 MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11, 60 MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12, 61 MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13, 62 MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14, 63 MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15, 64 MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16, 65 MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17, 66 MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18, 67 MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19, 68 MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20, 69 MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21, 70 MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22, 71 MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23, 72 }; 73 74 imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); 75 } 76 77 static void lcd_enable(void) 78 { 79 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 80 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; 81 82 /* Set LDB_DI0 as clock source for IPU_DI0 */ 83 clrsetbits_le32(&mxc_ccm->cscmr2, 84 MXC_CCM_CSCMR2_DI0_CLK_SEL_MASK, 85 MXC_CCM_CSCMR2_DI0_CLK_SEL( 86 MXC_CCM_CSCMR2_DI0_CLK_SEL_LDB_DI0_CLK)); 87 88 /* Turn on IPU LDB DI0 clocks */ 89 setbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_LDB_DI0(3)); 90 91 /* Turn on IPU DI0 clocks */ 92 setbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_IPU_DI0(3)); 93 94 /* Configure LDB */ 95 writel(IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG | 96 IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT | 97 IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0, 98 &iomux->gpr[2]); 99 100 /* Enable backlights */ 101 pwm_init(1, 0, 0); 102 103 /* duty cycle 5000000ns, period: 5000000ns */ 104 pwm_config(1, 5000000, 5000000); 105 106 /* Backlight Power */ 107 gpio_direction_output(BACKLIGHT_ENABLE, 1); 108 109 pwm_enable(1); 110 } 111 112 static int do_lcd_enable(cmd_tbl_t *cmdtp, int flag, int argc, 113 char * const argv[]) 114 { 115 lcd_enable(); 116 return 0; 117 } 118 119 U_BOOT_CMD( 120 ppd_lcd_enable, 1, 1, do_lcd_enable, 121 "enable PPD LCD", 122 "no parameters" 123 ); 124 125 int board_video_skip(void) 126 { 127 int ret; 128 129 ret = ipuv3_fb_init(&nv_spwg, 0, IPU_PIX_FMT_RGB24); 130 if (ret) 131 printf("Display cannot be configured: %d\n", ret); 132 133 return ret; 134 } 135
