1 # SPDX-License-Identifier: GPL-2.0+ 2 # 3 # (C) Copyright 2009-2012 4 # Wojciech Dubowik <wojciech.dubowik (a] neratec.com> 5 # Luka Perkov <luka (a] openwrt.org> 6 # Refer doc/README.kwbimage for more details about how-to configure 7 # and create kirkwood boot image 8 # 9 10 # Boot Media configurations 11 BOOT_FROM nand 12 NAND_ECC_MODE default 13 NAND_PAGE_SIZE 0x0800 14 15 # SOC registers configuration using bootrom header extension 16 # Maximum KWBIMAGE_MAX_CONFIG configurations allowed 17 18 # Configure RGMII-0 interface pad voltage to 1.8V 19 DATA 0xffd100e0 0x1b1b1b9b 20 21 # Dram initalization for SINGLE x16 CL=5 @ 400MHz 22 DATA 0xffd01400 0x43000c30 # DDR Configuration register 23 # bit13-0: 0xc30, (3120 DDR2 clks refresh rate) 24 # bit23-14: 0x0, 25 # bit24: 0x1, enable exit self refresh mode on DDR access 26 # bit25: 0x1, required 27 # bit29-26: 0x0, 28 # bit31-30: 0x1, 29 30 DATA 0xffd01404 0x37543000 # DDR Controller Control Low 31 # bit4: 0x0, addr/cmd in smame cycle 32 # bit5: 0x0, clk is driven during self refresh, we don't care for APX 33 # bit6: 0x0, use recommended falling edge of clk for addr/cmd 34 # bit14: 0x0, input buffer always powered up 35 # bit18: 0x1, cpu lock transaction enabled 36 # bit23-20: 0x5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 37 # bit27-24: 0x7, CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM 38 # bit30-28: 0x3, required 39 # bit31: 0x0, no additional STARTBURST delay 40 41 DATA 0xffd01408 0x22125451 # DDR Timing (Low) (active cycles value +1) 42 # bit3-0: TRAS lsbs 43 # bit7-4: TRCD 44 # bit11-8: TRP 45 # bit15-12: TWR 46 # bit19-16: TWTR 47 # bit20: TRAS msb 48 # bit23-21: 0x0 49 # bit27-24: TRRD 50 # bit31-28: TRTP 51 52 DATA 0xffd0140c 0x00000a33 # DDR Timing (High) 53 # bit6-0: TRFC 54 # bit8-7: TR2R 55 # bit10-9: TR2W 56 # bit12-11: TW2W 57 # bit31-13: 0x0, required 58 59 DATA 0xffd01410 0x000000cc # DDR Address Control 60 # bit1-0: 00, Cs0width (x8) 61 # bit3-2: 11, Cs0size (1Gb) 62 # bit5-4: 00, Cs1width (x8) 63 # bit7-6: 11, Cs1size (1Gb) 64 # bit9-8: 00, Cs2width (nonexistent) 65 # bit11-10: 00, Cs2size (nonexistent) 66 # bit13-12: 00, Cs3width (nonexistent) 67 # bit15-14: 00, Cs3size (nonexistent) 68 # bit16: 0, Cs0AddrSel 69 # bit17: 0, Cs1AddrSel 70 # bit18: 0, Cs2AddrSel 71 # bit19: 0, Cs3AddrSel 72 # bit31-20: 0x0, required 73 74 DATA 0xffd01414 0x00000000 # DDR Open Pages Control 75 # bit0: 0, OpenPage enabled 76 # bit31-1: 0x0, required 77 78 DATA 0xffd01418 0x00000000 # DDR Operation 79 # bit3-0: 0x0, DDR cmd 80 # bit31-4: 0x0, required 81 82 DATA 0xffd0141c 0x00000c52 # DDR Mode 83 # bit2-0: 0x2, BurstLen=2 required 84 # bit3: 0x0, BurstType=0 required 85 # bit6-4: 0x4, CL=5 86 # bit7: 0x0, TestMode=0 normal 87 # bit8: 0x0, DLL reset=0 normal 88 # bit11-9: 0x6, auto-precharge write recovery 89 # bit12: 0x0, PD must be zero 90 # bit31-13: 0x0, required 91 92 DATA 0xffd01420 0x00000040 # DDR Extended Mode 93 # bit0: 0, DDR DLL enabled 94 # bit1: 0, DDR drive strenght normal 95 # bit2: 0, DDR ODT control lsd (disabled) 96 # bit5-3: 0x0, required 97 # bit6: 1, DDR ODT control msb, (disabled) 98 # bit9-7: 0x0, required 99 # bit10: 0, differential DQS enabled 100 # bit11: 0, required 101 # bit12: 0, DDR output buffer enabled 102 # bit31-13: 0x0, required 103 104 DATA 0xffd01424 0x0000f17f # DDR Controller Control High 105 # bit2-0: 0x7, required 106 # bit3: 0x1, MBUS Burst Chop disabled 107 # bit6-4: 0x7, required 108 # bit7: 0x0, 109 # bit8: 0x1, add writepath sample stage, must be 1 for DDR freq >= 300MHz 110 # bit9: 0x0, no half clock cycle addition to dataout 111 # bit10: 0x0, 1/4 clock cycle skew enabled for addr/ctl signals 112 # bit11: 0x0, 1/4 clock cycle skew disabled for write mesh 113 # bit15-12: 0xf, required 114 # bit31-16: 0x0, required 115 116 DATA 0xffd01428 0x00085520 # DDR2 ODT Read Timing (default values) 117 DATA 0xffd0147c 0x00008552 # DDR2 ODT Write Timing (default values) 118 119 DATA 0xffd01500 0x00000000 # CS[0]n Base address to 0x0 120 DATA 0xffd01504 0x0ffffff1 # CS[0]n Size 121 # bit0: 0x1, Window enabled 122 # bit1: 0x0, Write Protect disabled 123 # bit3-2: 0x0, CS0 hit selected 124 # bit23-4: 0xfffff, required 125 # bit31-24: 0x0f, Size (i.e. 256MB) 126 127 DATA 0xffd01508 0x00000000 # CS[1]n Base address to 256Mb 128 DATA 0xffd0150c 0x00000000 # CS[1]n Size, window disabled 129 130 DATA 0xffd01514 0x00000000 # CS[2]n Size, window disabled 131 DATA 0xffd0151c 0x00000000 # CS[3]n Size, window disabled 132 133 DATA 0xffd01494 0x00030000 # DDR ODT Control (Low) 134 # bit3-0: ODT0Rd, MODT[0] asserted during read from DRAM CS1 135 # bit7-4: ODT0Rd, MODT[0] asserted during read from DRAM CS0 136 # bit19-16:2, ODT0Wr, MODT[0] asserted during write to DRAM CS1 137 # bit23-20:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0 138 139 DATA 0xffd01498 0x00000000 # DDR ODT Control (High) 140 # bit1-0: 0x0, ODT0 controlled by ODT Control (low) register above 141 # bit3-2: 0x1, ODT1 active NEVER! 142 # bit31-4: 0x0, required 143 144 DATA 0xffd0149c 0x0000e803 # CPU ODT Control 145 DATA 0xffd01480 0x00000001 # DDR Initialization Control 146 # bit0: 0x1, enable DDR init upon this register write 147 148 # End of Header extension 149 DATA 0x0 0x0 150
