1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * PPC-AG BG0900 board 4 * 5 * Copyright (C) 2013 Marek Vasut <marex (at) denx.de> 6 */ 7 8 #include <common.h> 9 #include <asm/gpio.h> 10 #include <asm/io.h> 11 #include <asm/arch/imx-regs.h> 12 #include <asm/arch/iomux-mx28.h> 13 #include <asm/arch/clock.h> 14 #include <asm/arch/sys_proto.h> 15 #include <linux/mii.h> 16 #include <miiphy.h> 17 #include <netdev.h> 18 #include <errno.h> 19 20 DECLARE_GLOBAL_DATA_PTR; 21 22 /* 23 * Functions 24 */ 25 int board_early_init_f(void) 26 { 27 /* IO0 clock at 480MHz */ 28 mxs_set_ioclk(MXC_IOCLK0, 480000); 29 /* IO1 clock at 480MHz */ 30 mxs_set_ioclk(MXC_IOCLK1, 480000); 31 32 /* SSP2 clock at 160MHz */ 33 mxs_set_sspclk(MXC_SSPCLK2, 160000, 0); 34 35 return 0; 36 } 37 38 int dram_init(void) 39 { 40 return mxs_dram_init(); 41 } 42 43 int board_init(void) 44 { 45 /* Adress of boot parameters */ 46 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; 47 48 return 0; 49 } 50 51 #ifdef CONFIG_CMD_NET 52 int board_eth_init(bd_t *bis) 53 { 54 struct mxs_clkctrl_regs *clkctrl_regs = 55 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; 56 struct eth_device *dev; 57 int ret; 58 59 ret = cpu_eth_init(bis); 60 61 /* BG0900 uses ENET_CLK PAD to drive FEC clock */ 62 writel(CLKCTRL_ENET_TIME_SEL_RMII_CLK | CLKCTRL_ENET_CLK_OUT_EN, 63 &clkctrl_regs->hw_clkctrl_enet); 64 65 /* Reset FEC PHYs */ 66 gpio_direction_output(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 0); 67 udelay(200); 68 gpio_set_value(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 1); 69 70 ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE); 71 if (ret) { 72 puts("FEC MXS: Unable to init FEC0\n"); 73 return ret; 74 } 75 76 dev = eth_get_dev_by_name("FEC0"); 77 if (!dev) { 78 puts("FEC MXS: Unable to get FEC0 device entry\n"); 79 return -EINVAL; 80 } 81 82 return ret; 83 } 84 85 #endif 86
