1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2007-2008 4 * Nobuhiro Iwamatsu <iwamatsu (at) nigauri.org> 5 * 6 * Copyright (C) 2007 7 * Kenati Technologies, Inc. 8 * 9 * board/MigoR/lowlevel_init.S 10 */ 11 12 #include <config.h> 13 14 #include <asm/processor.h> 15 #include <asm/macro.h> 16 17 /* 18 * Board specific low level init code, called _very_ early in the 19 * startup sequence. Relocation to SDRAM has not happened yet, no 20 * stack is available, bss section has not been initialised, etc. 21 * 22 * (Note: As no stack is available, no subroutines can be called...). 23 */ 24 25 .global lowlevel_init 26 27 .text 28 .align 2 29 30 lowlevel_init: 31 write32 CCR_A, CCR_D ! Address of Cache Control Register 32 ! Instruction Cache Invalidate 33 34 write32 MMUCR_A, MMUCR_D ! Address of MMU Control Register 35 ! TI == TLB Invalidate bit 36 37 write32 MSTPCR0_A, MSTPCR0_D ! Address of Power Control Register 0 38 39 write32 MSTPCR2_A, MSTPCR2_D ! Address of Power Control Register 2 40 41 write16 PFC_PULCR_A, PFC_PULCR_D 42 43 write16 PFC_DRVCR_A, PFC_DRVCR_D 44 45 write16 SBSCR_A, SBSCR_D 46 47 write16 PSCR_A, PSCR_D 48 49 write16 RWTCSR_A, RWTCSR_D_1 ! 0xA4520004 (Watchdog Control / Status Register) 50 ! 0xA507 -> timer_STOP / WDT_CLK = max 51 52 write16 RWTCNT_A, RWTCNT_D ! 0xA4520000 (Watchdog Count Register) 53 ! 0x5A00 -> Clear 54 55 write16 RWTCSR_A, RWTCSR_D_2 ! 0xA4520004 (Watchdog Control / Status Register) 56 ! 0xA504 -> timer_STOP / CLK = 500ms 57 58 write32 DLLFRQ_A, DLLFRQ_D ! 20080115 59 ! 20080115 60 61 write32 FRQCR_A, FRQCR_D ! 0xA4150000 Frequency control register 62 ! 20080115 63 64 write32 CCR_A, CCR_D_2 ! Address of Cache Control Register 65 ! ?? 66 67 bsc_init: 68 write32 CMNCR_A, CMNCR_D 69 70 write32 CS0BCR_A, CS0BCR_D 71 72 write32 CS4BCR_A, CS4BCR_D 73 74 write32 CS5ABCR_A, CS5ABCR_D 75 76 write32 CS5BBCR_A, CS5BBCR_D 77 78 write32 CS6ABCR_A, CS6ABCR_D 79 80 write32 CS0WCR_A, CS0WCR_D 81 82 write32 CS4WCR_A, CS4WCR_D 83 84 write32 CS5AWCR_A, CS5AWCR_D 85 86 write32 CS5BWCR_A, CS5BWCR_D 87 88 write32 CS6AWCR_A, CS6AWCR_D 89 90 ! SDRAM initialization 91 write32 SDCR_A, SDCR_D 92 93 write32 SDWCR_A, SDWCR_D 94 95 write32 SDPCR_A, SDPCR_D 96 97 write32 RTCOR_A, RTCOR_D 98 99 write32 RTCNT_A, RTCNT_D 100 101 write32 RTCSR_A, RTCSR_D 102 103 write32 RFCR_A, RFCR_D 104 105 write8 SDMR3_A, SDMR3_D 106 107 ! BL bit off (init = ON) (?!?) 108 109 stc sr, r0 ! BL bit off(init=ON) 110 mov.l SR_MASK_D, r1 111 and r1, r0 112 ldc r0, sr 113 114 rts 115 mov #0, r0 116 117 .align 4 118 119 CCR_A: .long CCR 120 MMUCR_A: .long MMUCR 121 MSTPCR0_A: .long MSTPCR0 122 MSTPCR2_A: .long MSTPCR2 123 PFC_PULCR_A: .long PULCR 124 PFC_DRVCR_A: .long DRVCR 125 SBSCR_A: .long SBSCR 126 PSCR_A: .long PSCR 127 RWTCSR_A: .long RWTCSR 128 RWTCNT_A: .long RWTCNT 129 FRQCR_A: .long FRQCR 130 PLLCR_A: .long PLLCR 131 DLLFRQ_A: .long DLLFRQ 132 133 CCR_D: .long 0x00000800 134 CCR_D_2: .long 0x00000103 135 MMUCR_D: .long 0x00000004 136 MSTPCR0_D: .long 0x00001001 137 MSTPCR2_D: .long 0xffffffff 138 PFC_PULCR_D: .long 0x6000 139 PFC_DRVCR_D: .long 0x0464 140 FRQCR_D: .long 0x07033639 141 PLLCR_D: .long 0x00005000 142 DLLFRQ_D: .long 0x000004F6 143 144 CMNCR_A: .long CMNCR 145 CMNCR_D: .long 0x0000001B 146 CS0BCR_A: .long CS0BCR 147 CS0BCR_D: .long 0x24920400 148 CS4BCR_A: .long CS4BCR 149 CS4BCR_D: .long 0x00003400 150 CS5ABCR_A: .long CS5ABCR 151 CS5ABCR_D: .long 0x24920400 152 CS5BBCR_A: .long CS5BBCR 153 CS5BBCR_D: .long 0x24920400 154 CS6ABCR_A: .long CS6ABCR 155 CS6ABCR_D: .long 0x24920400 156 157 CS0WCR_A: .long CS0WCR 158 CS0WCR_D: .long 0x00000380 159 CS4WCR_A: .long CS4WCR 160 CS4WCR_D: .long 0x00110080 161 CS5AWCR_A: .long CS5AWCR 162 CS5AWCR_D: .long 0x00000300 163 CS5BWCR_A: .long CS5BWCR 164 CS5BWCR_D: .long 0x00000300 165 CS6AWCR_A: .long CS6AWCR 166 CS6AWCR_D: .long 0x00000300 167 168 SDCR_A: .long SBSC_SDCR 169 SDCR_D: .long 0x80160809 170 SDWCR_A: .long SBSC_SDWCR 171 SDWCR_D: .long 0x0014450C 172 SDPCR_A: .long SBSC_SDPCR 173 SDPCR_D: .long 0x00000087 174 RTCOR_A: .long SBSC_RTCOR 175 RTCNT_A: .long SBSC_RTCNT 176 RTCNT_D: .long 0xA55A0012 177 RTCOR_D: .long 0xA55A001C 178 RTCSR_A: .long SBSC_RTCSR 179 RFCR_A: .long SBSC_RFCR 180 RFCR_D: .long 0xA55A0221 181 RTCSR_D: .long 0xA55A009a 182 SDMR3_A: .long 0xFE581180 183 SDMR3_D: .long 0x0 184 185 SR_MASK_D: .long 0xEFFFFF0F 186 187 .align 2 188 189 SBSCR_D: .word 0x0044 190 PSCR_D: .word 0x0000 191 RWTCSR_D_1: .word 0xA507 192 RWTCSR_D_2: .word 0xA504 193 RWTCNT_D: .word 0x5A00 194
