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      1 // SPDX-License-Identifier: GPL-2.0
      2 /*
      3  * board/renesas/gose/gose.c
      4  *
      5  * Copyright (C) 2014 Renesas Electronics Corporation
      6  */
      7 
      8 #include <common.h>
      9 #include <malloc.h>
     10 #include <dm.h>
     11 #include <dm/platform_data/serial_sh.h>
     12 #include <environment.h>
     13 #include <asm/processor.h>
     14 #include <asm/mach-types.h>
     15 #include <asm/io.h>
     16 #include <linux/errno.h>
     17 #include <asm/arch/sys_proto.h>
     18 #include <asm/gpio.h>
     19 #include <asm/arch/rmobile.h>
     20 #include <asm/arch/rcar-mstp.h>
     21 #include <asm/arch/sh_sdhi.h>
     22 #include <netdev.h>
     23 #include <miiphy.h>
     24 #include <i2c.h>
     25 #include "qos.h"
     26 
     27 DECLARE_GLOBAL_DATA_PTR;
     28 
     29 #define CLK2MHZ(clk)	(clk / 1000 / 1000)
     30 void s_init(void)
     31 {
     32 	struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
     33 	struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
     34 	u32 stc;
     35 
     36 	/* Watchdog init */
     37 	writel(0xA5A5A500, &rwdt->rwtcsra);
     38 	writel(0xA5A5A500, &swdt->swtcsra);
     39 
     40 	/* CPU frequency setting. Set to 1.5GHz */
     41 	stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT;
     42 	clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
     43 
     44 	/* QoS */
     45 	qos_init();
     46 }
     47 
     48 #define TMU0_MSTP125	BIT(25)
     49 
     50 #define SD1CKCR		0xE6150078
     51 #define SD2CKCR		0xE615026C
     52 #define SD_97500KHZ	0x7
     53 
     54 int board_early_init_f(void)
     55 {
     56 	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
     57 
     58 	/*
     59 	 * SD0 clock is set to 97.5MHz by default.
     60 	 * Set SD1 and SD2 to the 97.5MHz as well.
     61 	 */
     62 	writel(SD_97500KHZ, SD1CKCR);
     63 	writel(SD_97500KHZ, SD2CKCR);
     64 
     65 	return 0;
     66 }
     67 
     68 #define ETHERNET_PHY_RESET	176	/* GPIO 5 22 */
     69 
     70 int board_init(void)
     71 {
     72 	/* adress of boot parameters */
     73 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
     74 
     75 	/* Force ethernet PHY out of reset */
     76 	gpio_request(ETHERNET_PHY_RESET, "phy_reset");
     77 	gpio_direction_output(ETHERNET_PHY_RESET, 0);
     78 	mdelay(10);
     79 	gpio_direction_output(ETHERNET_PHY_RESET, 1);
     80 
     81 	return 0;
     82 }
     83 
     84 int dram_init(void)
     85 {
     86 	if (fdtdec_setup_memory_size() != 0)
     87 		return -EINVAL;
     88 
     89 	return 0;
     90 }
     91 
     92 int dram_init_banksize(void)
     93 {
     94 	fdtdec_setup_memory_banksize();
     95 
     96 	return 0;
     97 }
     98 
     99 /* KSZ8041RNLI */
    100 #define PHY_CONTROL1		0x1E
    101 #define PHY_LED_MODE		0xC0000
    102 #define PHY_LED_MODE_ACK	0x4000
    103 int board_phy_config(struct phy_device *phydev)
    104 {
    105 	int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
    106 	ret &= ~PHY_LED_MODE;
    107 	ret |= PHY_LED_MODE_ACK;
    108 	ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);
    109 
    110 	return 0;
    111 }
    112 
    113 void reset_cpu(ulong addr)
    114 {
    115 	struct udevice *dev;
    116 	const u8 pmic_bus = 6;
    117 	const u8 pmic_addr = 0x58;
    118 	u8 data;
    119 	int ret;
    120 
    121 	ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev);
    122 	if (ret)
    123 		hang();
    124 
    125 	ret = dm_i2c_read(dev, 0x13, &data, 1);
    126 	if (ret)
    127 		hang();
    128 
    129 	data |= BIT(1);
    130 
    131 	ret = dm_i2c_write(dev, 0x13, &data, 1);
    132 	if (ret)
    133 		hang();
    134 }
    135 
    136 enum env_location env_get_location(enum env_operation op, int prio)
    137 {
    138 	const u32 load_magic = 0xb33fc0de;
    139 
    140 	/* Block environment access if loaded using JTAG */
    141 	if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) &&
    142 	    (op != ENVOP_INIT))
    143 		return ENVL_UNKNOWN;
    144 
    145 	if (prio)
    146 		return ENVL_UNKNOWN;
    147 
    148 	return ENVL_SPI_FLASH;
    149 }
    150