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      1 // SPDX-License-Identifier: GPL-2.0
      2 /*
      3  * board/renesas/koelsch/koelsch.c
      4  *
      5  * Copyright (C) 2013 Renesas Electronics Corporation
      6  *
      7  */
      8 
      9 #include <common.h>
     10 #include <malloc.h>
     11 #include <dm.h>
     12 #include <dm/platform_data/serial_sh.h>
     13 #include <environment.h>
     14 #include <asm/processor.h>
     15 #include <asm/mach-types.h>
     16 #include <asm/io.h>
     17 #include <linux/errno.h>
     18 #include <asm/arch/sys_proto.h>
     19 #include <asm/gpio.h>
     20 #include <asm/arch/rmobile.h>
     21 #include <asm/arch/rcar-mstp.h>
     22 #include <asm/arch/sh_sdhi.h>
     23 #include <netdev.h>
     24 #include <miiphy.h>
     25 #include <i2c.h>
     26 #include <div64.h>
     27 #include "qos.h"
     28 
     29 DECLARE_GLOBAL_DATA_PTR;
     30 
     31 #define CLK2MHZ(clk)	(clk / 1000 / 1000)
     32 void s_init(void)
     33 {
     34 	struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
     35 	struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
     36 	u32 stc;
     37 
     38 	/* Watchdog init */
     39 	writel(0xA5A5A500, &rwdt->rwtcsra);
     40 	writel(0xA5A5A500, &swdt->swtcsra);
     41 
     42 	/* CPU frequency setting. Set to 1.5GHz */
     43 	stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT;
     44 	clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
     45 
     46 	/* QoS */
     47 	qos_init();
     48 }
     49 
     50 #define TMU0_MSTP125	BIT(25)
     51 
     52 #define SD1CKCR		0xE6150078
     53 #define SD2CKCR		0xE615026C
     54 #define SD_97500KHZ	0x7
     55 
     56 int board_early_init_f(void)
     57 {
     58 	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
     59 
     60 	/*
     61 	 * SD0 clock is set to 97.5MHz by default.
     62 	 * Set SD1 and SD2 to the 97.5MHz as well.
     63 	 */
     64 	writel(SD_97500KHZ, SD1CKCR);
     65 	writel(SD_97500KHZ, SD2CKCR);
     66 
     67 	return 0;
     68 }
     69 
     70 #define ETHERNET_PHY_RESET	176	/* GPIO 5 22 */
     71 
     72 int board_init(void)
     73 {
     74 	/* adress of boot parameters */
     75 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
     76 
     77 	/* Force ethernet PHY out of reset */
     78 	gpio_request(ETHERNET_PHY_RESET, "phy_reset");
     79 	gpio_direction_output(ETHERNET_PHY_RESET, 0);
     80 	mdelay(10);
     81 	gpio_direction_output(ETHERNET_PHY_RESET, 1);
     82 
     83 	return 0;
     84 }
     85 
     86 int dram_init(void)
     87 {
     88 	if (fdtdec_setup_memory_size() != 0)
     89 		return -EINVAL;
     90 
     91 	return 0;
     92 }
     93 
     94 int dram_init_banksize(void)
     95 {
     96 	fdtdec_setup_memory_banksize();
     97 
     98 	return 0;
     99 }
    100 
    101 /* Koelsch has KSZ8041NL/RNL */
    102 #define PHY_CONTROL1		0x1E
    103 #define PHY_LED_MODE		0xC0000
    104 #define PHY_LED_MODE_ACK	0x4000
    105 int board_phy_config(struct phy_device *phydev)
    106 {
    107 	int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
    108 	ret &= ~PHY_LED_MODE;
    109 	ret |= PHY_LED_MODE_ACK;
    110 	ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);
    111 
    112 	return 0;
    113 }
    114 
    115 void reset_cpu(ulong addr)
    116 {
    117 	struct udevice *dev;
    118 	const u8 pmic_bus = 6;
    119 	const u8 pmic_addr = 0x58;
    120 	u8 data;
    121 	int ret;
    122 
    123 	ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev);
    124 	if (ret)
    125 		hang();
    126 
    127 	ret = dm_i2c_read(dev, 0x13, &data, 1);
    128 	if (ret)
    129 		hang();
    130 
    131 	data |= BIT(1);
    132 
    133 	ret = dm_i2c_write(dev, 0x13, &data, 1);
    134 	if (ret)
    135 		hang();
    136 }
    137 
    138 enum env_location env_get_location(enum env_operation op, int prio)
    139 {
    140 	const u32 load_magic = 0xb33fc0de;
    141 
    142 	/* Block environment access if loaded using JTAG */
    143 	if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) &&
    144 	    (op != ENVOP_INIT))
    145 		return ENVL_UNKNOWN;
    146 
    147 	if (prio)
    148 		return ENVL_UNKNOWN;
    149 
    150 	return ENVL_SPI_FLASH;
    151 }
    152