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      1 // SPDX-License-Identifier: GPL-2.0
      2 /*
      3  * board/renesas/koelsch/koelsch_spl.c
      4  *
      5  * Copyright (C) 2018 Marek Vasut <marek.vasut (at) gmail.com>
      6  */
      7 
      8 #include <common.h>
      9 #include <malloc.h>
     10 #include <dm/platform_data/serial_sh.h>
     11 #include <asm/processor.h>
     12 #include <asm/mach-types.h>
     13 #include <asm/io.h>
     14 #include <linux/errno.h>
     15 #include <asm/arch/sys_proto.h>
     16 #include <asm/gpio.h>
     17 #include <asm/arch/rmobile.h>
     18 #include <asm/arch/rcar-mstp.h>
     19 
     20 #include <spl.h>
     21 
     22 #define TMU0_MSTP125	BIT(25)
     23 #define SCIF0_MSTP721	BIT(21)
     24 #define QSPI_MSTP917	BIT(17)
     25 
     26 #define SD2CKCR		0xE615026C
     27 #define SD_97500KHZ	0x7
     28 
     29 struct reg_config {
     30 	u16	off;
     31 	u32	val;
     32 };
     33 
     34 static void dbsc_wait(u16 reg)
     35 {
     36 	static const u32 dbsc3_0_base = DBSC3_0_BASE;
     37 	static const u32 dbsc3_1_base = DBSC3_0_BASE + 0x10000;
     38 
     39 	while (!(readl(dbsc3_0_base + reg) & BIT(0)))
     40 		;
     41 
     42 	while (!(readl(dbsc3_1_base + reg) & BIT(0)))
     43 		;
     44 }
     45 
     46 static void spl_init_sys(void)
     47 {
     48 	u32 r0 = 0;
     49 
     50 	writel(0xa5a5a500, 0xe6020004);
     51 	writel(0xa5a5a500, 0xe6030004);
     52 
     53 	asm volatile(
     54 		/* ICIALLU - Invalidate I$ to PoU */
     55 		"mcr	15, 0, %0, cr7, cr5, 0	\n"
     56 		/* BPIALL - Invalidate branch predictors */
     57 		"mcr	15, 0, %0, cr7, cr5, 6	\n"
     58 		/* Set SCTLR[IZ] */
     59 		"mrc	15, 0, %0, cr1, cr0, 0	\n"
     60 		"orr	%0, #0x1800		\n"
     61 		"mcr	15, 0, %0, cr1, cr0, 0	\n"
     62 		"isb	sy			\n"
     63 		:"=r"(r0));
     64 }
     65 
     66 static void spl_init_pfc(void)
     67 {
     68 	static const struct reg_config pfc_with_unlock[] = {
     69 		{ 0x0090, 0x60000000 },
     70 		{ 0x0094, 0x60000000 },
     71 		{ 0x0098, 0x00800200 },
     72 		{ 0x009c, 0x00000000 },
     73 		{ 0x0020, 0x00000000 },
     74 		{ 0x0024, 0x00000000 },
     75 		{ 0x0028, 0x000244c8 },
     76 		{ 0x002c, 0x00000000 },
     77 		{ 0x0030, 0x00002400 },
     78 		{ 0x0034, 0x01520000 },
     79 		{ 0x0038, 0x00724003 },
     80 		{ 0x003c, 0x00000000 },
     81 		{ 0x0040, 0x00000000 },
     82 		{ 0x0044, 0x00000000 },
     83 		{ 0x0048, 0x00000000 },
     84 		{ 0x004c, 0x00000000 },
     85 		{ 0x0050, 0x00000000 },
     86 		{ 0x0054, 0x00000000 },
     87 		{ 0x0058, 0x00000000 },
     88 		{ 0x005c, 0x00000000 },
     89 		{ 0x0160, 0x00000000 },
     90 		{ 0x0004, 0xffffffff },
     91 		{ 0x0008, 0x00ec3fff },
     92 		{ 0x000c, 0x3bc001e7 },
     93 		{ 0x0010, 0x5bffffff },
     94 		{ 0x0014, 0x1ffffffb },
     95 		{ 0x0018, 0x01bffff0 },
     96 		{ 0x001c, 0xcf7fffff },
     97 		{ 0x0074, 0x0381fc00 },
     98 	};
     99 
    100 	static const struct reg_config pfc_without_unlock[] = {
    101 		{ 0x0100, 0xffffffdf },
    102 		{ 0x0104, 0xc883c3ff },
    103 		{ 0x0108, 0x1201f3c9 },
    104 		{ 0x010c, 0x00000000 },
    105 		{ 0x0110, 0xffffeb04 },
    106 		{ 0x0114, 0xc003ffff },
    107 		{ 0x0118, 0x0800000f },
    108 		{ 0x011c, 0x001800f0 },
    109 	};
    110 
    111 	static const u32 pfc_base = 0xe6060000;
    112 
    113 	unsigned int i;
    114 
    115 	for (i = 0; i < ARRAY_SIZE(pfc_with_unlock); i++) {
    116 		writel(~pfc_with_unlock[i].val, pfc_base);
    117 		writel(pfc_with_unlock[i].val,
    118 		       pfc_base | pfc_with_unlock[i].off);
    119 	}
    120 
    121 	for (i = 0; i < ARRAY_SIZE(pfc_without_unlock); i++)
    122 		writel(pfc_without_unlock[i].val,
    123 		       pfc_base | pfc_without_unlock[i].off);
    124 }
    125 
    126 static void spl_init_gpio(void)
    127 {
    128 	static const u16 gpio_offs[] = {
    129 		0x1000, 0x2000, 0x3000, 0x4000, 0x5000, 0x5400, 0x5800
    130 	};
    131 
    132 	static const struct reg_config gpio_set[] = {
    133 		{ 0x2000, 0x04381000 },
    134 		{ 0x5000, 0x00000000 },
    135 		{ 0x5800, 0x000e0000 },
    136 
    137 	};
    138 
    139 	static const struct reg_config gpio_clr[] = {
    140 		{ 0x1000, 0x00000000 },
    141 		{ 0x2000, 0x04381010 },
    142 		{ 0x3000, 0x00000000 },
    143 		{ 0x4000, 0x00000000 },
    144 		{ 0x5000, 0x00400000 },
    145 		{ 0x5400, 0x00000000 },
    146 		{ 0x5800, 0x000e0380 },
    147 	};
    148 
    149 	static const u32 gpio_base = 0xe6050000;
    150 
    151 	unsigned int i;
    152 
    153 	for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
    154 		writel(0, gpio_base | 0x20 | gpio_offs[i]);
    155 
    156 	for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
    157 		writel(0, gpio_base | 0x00 | gpio_offs[i]);
    158 
    159 	for (i = 0; i < ARRAY_SIZE(gpio_set); i++)
    160 		writel(gpio_set[i].val, gpio_base | 0x08 | gpio_set[i].off);
    161 
    162 	for (i = 0; i < ARRAY_SIZE(gpio_clr); i++)
    163 		writel(gpio_clr[i].val, gpio_base | 0x04 | gpio_clr[i].off);
    164 }
    165 
    166 static void spl_init_lbsc(void)
    167 {
    168 	static const struct reg_config lbsc_config[] = {
    169 		{ 0x00, 0x00000020 },
    170 		{ 0x08, 0x00002020 },
    171 		{ 0x30, 0x2a103320 },
    172 		{ 0x38, 0xff70ff70 },
    173 	};
    174 
    175 	static const u16 lbsc_offs[] = {
    176 		0x80, 0x84, 0x88, 0x8c, 0xa0, 0xc0, 0xc4, 0xc8, 0x180
    177 	};
    178 
    179 	static const u32 lbsc_base = 0xfec00200;
    180 
    181 	unsigned int i;
    182 
    183 	for (i = 0; i < ARRAY_SIZE(lbsc_config); i++) {
    184 		writel(lbsc_config[i].val,
    185 		       lbsc_base | lbsc_config[i].off);
    186 		writel(lbsc_config[i].val,
    187 		       lbsc_base | (lbsc_config[i].off + 4));
    188 	}
    189 
    190 	for (i = 0; i < ARRAY_SIZE(lbsc_offs); i++)
    191 		writel(0, lbsc_base | lbsc_offs[i]);
    192 }
    193 
    194 static void spl_init_dbsc(void)
    195 {
    196 	static const struct reg_config dbsc_config1[] = {
    197 		{ 0x0018, 0x21000000 },
    198 		{ 0x0018, 0x11000000 },
    199 		{ 0x0018, 0x10000000 },
    200 		{ 0x0280, 0x0000a55a },
    201 		{ 0x0290, 0x00000010 },
    202 		{ 0x02a0, 0xf004649b },
    203 		{ 0x0020, 0x00000007 },
    204 		{ 0x0024, 0x0f030a02 },
    205 		{ 0x0030, 0x00000001 },
    206 		{ 0x00b0, 0x00000000 },
    207 		{ 0x0040, 0x0000000b },
    208 		{ 0x0044, 0x00000008 },
    209 		{ 0x0048, 0x00000000 },
    210 		{ 0x0050, 0x0000000b },
    211 		{ 0x0054, 0x000c000b },
    212 		{ 0x0058, 0x00000027 },
    213 		{ 0x005c, 0x0000001c },
    214 		{ 0x0060, 0x00000006 },
    215 		{ 0x0064, 0x00000020 },
    216 		{ 0x0068, 0x00000008 },
    217 		{ 0x006c, 0x0000000c },
    218 		{ 0x0070, 0x00000009 },
    219 		{ 0x0074, 0x00000012 },
    220 		{ 0x0078, 0x000000d0 },
    221 		{ 0x007c, 0x00140005 },
    222 		{ 0x0080, 0x00050004 },
    223 		{ 0x0084, 0x70233005 },
    224 		{ 0x0088, 0x000c0000 },
    225 		{ 0x008c, 0x00000300 },
    226 		{ 0x0090, 0x00000040 },
    227 		{ 0x0100, 0x00000001 },
    228 		{ 0x00c0, 0x00020001 },
    229 		{ 0x00c8, 0x20082008 },
    230 		{ 0x0380, 0x00020002 },
    231 		{ 0x0390, 0x0000001f },
    232 	};
    233 
    234 	static const struct reg_config dbsc_config5[] = {
    235 		{ 0x0244, 0x00000011 },
    236 		{ 0x0290, 0x00000006 },
    237 		{ 0x02a0, 0x0005c000 },
    238 		{ 0x0290, 0x00000003 },
    239 		{ 0x02a0, 0x0300c481 },
    240 		{ 0x0290, 0x00000023 },
    241 		{ 0x02a0, 0x00fdb6c0 },
    242 		{ 0x0290, 0x00000011 },
    243 		{ 0x02a0, 0x1000040b },
    244 		{ 0x0290, 0x00000012 },
    245 		{ 0x02a0, 0x9d9cbb66 },
    246 		{ 0x0290, 0x00000013 },
    247 		{ 0x02a0, 0x1a868400 },
    248 		{ 0x0290, 0x00000014 },
    249 		{ 0x02a0, 0x300214d8 },
    250 		{ 0x0290, 0x00000015 },
    251 		{ 0x02a0, 0x00000d70 },
    252 		{ 0x0290, 0x00000016 },
    253 		{ 0x02a0, 0x00000006 },
    254 		{ 0x0290, 0x00000017 },
    255 		{ 0x02a0, 0x00000018 },
    256 		{ 0x0290, 0x0000001a },
    257 		{ 0x02a0, 0x910035c7 },
    258 		{ 0x0290, 0x00000004 },
    259 	};
    260 
    261 	static const struct reg_config dbsc_config6[] = {
    262 		{ 0x0290, 0x00000001 },
    263 		{ 0x02a0, 0x00000181 },
    264 		{ 0x0018, 0x11000000 },
    265 		{ 0x0290, 0x00000004 },
    266 	};
    267 
    268 	static const struct reg_config dbsc_config7[] = {
    269 		{ 0x0290, 0x00000001 },
    270 		{ 0x02a0, 0x0000fe01 },
    271 		{ 0x0290, 0x00000004 },
    272 	};
    273 
    274 	static const struct reg_config dbsc_config8[] = {
    275 		{ 0x0304, 0x00000000 },
    276 		{ 0x00f4, 0x01004c20 },
    277 		{ 0x00f8, 0x014000aa },
    278 		{ 0x00e0, 0x00000140 },
    279 		{ 0x00e4, 0x00081860 },
    280 		{ 0x00e8, 0x00010000 },
    281 		{ 0x0014, 0x00000001 },
    282 		{ 0x0010, 0x00000001 },
    283 		{ 0x0280, 0x00000000 },
    284 	};
    285 
    286 	static const u32 dbsc3_0_base = DBSC3_0_BASE;
    287 	static const u32 dbsc3_1_base = DBSC3_0_BASE + 0x10000;
    288 	unsigned int i;
    289 
    290 	for (i = 0; i < ARRAY_SIZE(dbsc_config1); i++) {
    291 		writel(dbsc_config1[i].val, dbsc3_0_base | dbsc_config1[i].off);
    292 		writel(dbsc_config1[i].val, dbsc3_1_base | dbsc_config1[i].off);
    293 	}
    294 
    295 	dbsc_wait(0x240);
    296 
    297 	for (i = 0; i < ARRAY_SIZE(dbsc_config5); i++) {
    298 		writel(dbsc_config5[i].val, dbsc3_0_base | dbsc_config5[i].off);
    299 		writel(dbsc_config5[i].val, dbsc3_1_base | dbsc_config5[i].off);
    300 	}
    301 
    302 	dbsc_wait(0x2a0);
    303 
    304 	for (i = 0; i < ARRAY_SIZE(dbsc_config6); i++) {
    305 		writel(dbsc_config6[i].val, dbsc3_0_base | dbsc_config6[i].off);
    306 		writel(dbsc_config6[i].val, dbsc3_1_base | dbsc_config6[i].off);
    307 	}
    308 
    309 	dbsc_wait(0x2a0);
    310 
    311 	for (i = 0; i < ARRAY_SIZE(dbsc_config7); i++) {
    312 		writel(dbsc_config7[i].val, dbsc3_0_base | dbsc_config7[i].off);
    313 		writel(dbsc_config7[i].val, dbsc3_1_base | dbsc_config7[i].off);
    314 	}
    315 
    316 	dbsc_wait(0x2a0);
    317 
    318 	for (i = 0; i < ARRAY_SIZE(dbsc_config8); i++) {
    319 		writel(dbsc_config8[i].val, dbsc3_0_base | dbsc_config8[i].off);
    320 		writel(dbsc_config8[i].val, dbsc3_1_base | dbsc_config8[i].off);
    321 	}
    322 
    323 }
    324 
    325 static void spl_init_qspi(void)
    326 {
    327 	mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917);
    328 
    329 	static const u32 qspi_base = 0xe6b10000;
    330 
    331 	writeb(0x08, qspi_base + 0x00);
    332 	writeb(0x00, qspi_base + 0x01);
    333 	writeb(0x06, qspi_base + 0x02);
    334 	writeb(0x01, qspi_base + 0x0a);
    335 	writeb(0x00, qspi_base + 0x0b);
    336 	writeb(0x00, qspi_base + 0x0c);
    337 	writeb(0x00, qspi_base + 0x0d);
    338 	writeb(0x00, qspi_base + 0x0e);
    339 
    340 	writew(0xe080, qspi_base + 0x10);
    341 
    342 	writeb(0xc0, qspi_base + 0x18);
    343 	writeb(0x00, qspi_base + 0x18);
    344 	writeb(0x00, qspi_base + 0x08);
    345 	writeb(0x48, qspi_base + 0x00);
    346 }
    347 
    348 void board_init_f(ulong dummy)
    349 {
    350 	int i;
    351 
    352 	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
    353 	mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
    354 
    355 	/*
    356 	 * SD0 clock is set to 97.5MHz by default.
    357 	 * Set SD2 to the 97.5MHz as well.
    358 	 */
    359 	writel(SD_97500KHZ, SD2CKCR);
    360 
    361 	spl_init_sys();
    362 	spl_init_pfc();
    363 	spl_init_gpio();
    364 	spl_init_lbsc();
    365 
    366 	/* Unknown, likely ES1.0-specific delay */
    367 	for (i = 0; i < 100000; i++)
    368 		asm volatile("nop");
    369 
    370 	spl_init_dbsc();
    371 	spl_init_qspi();
    372 }
    373 
    374 void spl_board_init(void)
    375 {
    376 	/* UART clocks enabled and gd valid - init serial console */
    377 	preloader_console_init();
    378 }
    379 
    380 void board_boot_order(u32 *spl_boot_list)
    381 {
    382 	const u32 jtag_magic = 0x1337c0de;
    383 	const u32 load_magic = 0xb33fc0de;
    384 
    385 	/*
    386 	 * If JTAG probe sets special word at 0xe6300020, then it must
    387 	 * put U-Boot into RAM and SPL will start it from RAM.
    388 	 */
    389 	if (readl(CONFIG_SPL_TEXT_BASE + 0x20) == jtag_magic) {
    390 		printf("JTAG boot detected!\n");
    391 
    392 		while (readl(CONFIG_SPL_TEXT_BASE + 0x24) != load_magic)
    393 			;
    394 
    395 		spl_boot_list[0] = BOOT_DEVICE_RAM;
    396 		spl_boot_list[1] = BOOT_DEVICE_NONE;
    397 
    398 		return;
    399 	}
    400 
    401 	/* Boot from SPI NOR with YMODEM UART fallback. */
    402 	spl_boot_list[0] = BOOT_DEVICE_SPI;
    403 	spl_boot_list[1] = BOOT_DEVICE_UART;
    404 	spl_boot_list[2] = BOOT_DEVICE_NONE;
    405 }
    406 
    407 void reset_cpu(ulong addr)
    408 {
    409 }
    410