1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Machine Specific Values for TRATS board based on EXYNOS4210 4 * 5 * Copyright (C) 2011 Samsung Electronics 6 * Heungjun Kim <riverful.kim (at) samsung.com> 7 */ 8 9 #ifndef _TRATS_SETUP_H 10 #define _TRATS_SETUP_H 11 12 #include <config.h> 13 #include <asm/arch/cpu.h> 14 15 /* CLK_SRC_CPU: APLL(1), MPLL(1), CORE(0), HPM(0) */ 16 #define MUX_HPM_SEL_MOUTAPLL 0x0 17 #define MUX_HPM_SEL_SCLKMPLL 0x1 18 #define MUX_CORE_SEL_MOUTAPLL 0x0 19 #define MUX_CORE_SEL_SCLKMPLL 0x1 20 #define MUX_MPLL_SEL_FILPLL 0x0 21 #define MUX_MPLL_SEL_MOUTMPLLFOUT 0x1 22 #define MUX_APLL_SEL_FILPLL 0x0 23 #define MUX_APLL_SEL_MOUTMPLLFOUT 0x1 24 #define CLK_SRC_CPU_VAL ((MUX_HPM_SEL_MOUTAPLL << 20) \ 25 | (MUX_CORE_SEL_MOUTAPLL << 16) \ 26 | (MUX_MPLL_SEL_MOUTMPLLFOUT << 8)\ 27 | (MUX_APLL_SEL_MOUTMPLLFOUT << 0)) 28 29 /* CLK_DIV_CPU0 */ 30 #define APLL_RATIO 0x0 31 #define PCLK_DBG_RATIO 0x1 32 #define ATB_RATIO 0x3 33 #define PERIPH_RATIO 0x3 34 #define COREM1_RATIO 0x7 35 #define COREM0_RATIO 0x3 36 #define CORE_RATIO 0x0 37 #define CLK_DIV_CPU0_VAL ((APLL_RATIO << 24) \ 38 | (PCLK_DBG_RATIO << 20) \ 39 | (ATB_RATIO << 16) \ 40 | (PERIPH_RATIO << 12) \ 41 | (COREM1_RATIO << 8) \ 42 | (COREM0_RATIO << 4) \ 43 | (CORE_RATIO << 0)) 44 45 /* CLK_DIV_CPU1 */ 46 #define HPM_RATIO 0x0 47 #define COPY_RATIO 0x3 48 #define CLK_DIV_CPU1_VAL ((HPM_RATIO << 4) | (COPY_RATIO)) 49 50 /* CLK_DIV_DMC0 */ 51 #define CORE_TIMERS_RATIO 0x1 52 #define COPY2_RATIO 0x3 53 #define DMCP_RATIO 0x1 54 #define DMCD_RATIO 0x1 55 #define DMC_RATIO 0x1 56 #define DPHY_RATIO 0x1 57 #define ACP_PCLK_RATIO 0x1 58 #define ACP_RATIO 0x3 59 #define CLK_DIV_DMC0_VAL ((CORE_TIMERS_RATIO << 28) \ 60 | (COPY2_RATIO << 24) \ 61 | (DMCP_RATIO << 20) \ 62 | (DMCD_RATIO << 16) \ 63 | (DMC_RATIO << 12) \ 64 | (DPHY_RATIO << 8) \ 65 | (ACP_PCLK_RATIO << 4) \ 66 | (ACP_RATIO << 0)) 67 68 /* CLK_DIV_DMC1 */ 69 #define DPM_RATIO 0x1 70 #define DVSEM_RATIO 0x1 71 #define PWI_RATIO 0x1 72 #define CLK_DIV_DMC1_VAL ((DPM_RATIO << 24) \ 73 | (DVSEM_RATIO << 16) \ 74 | (PWI_RATIO << 8)) 75 76 /* CLK_SRC_TOP0 */ 77 #define MUX_ONENAND_SEL_ACLK_133 0x0 78 #define MUX_ONENAND_SEL_ACLK_160 0x1 79 #define MUX_ACLK_133_SEL_SCLKMPLL 0x0 80 #define MUX_ACLK_133_SEL_SCLKAPLL 0x1 81 #define MUX_ACLK_160_SEL_SCLKMPLL 0x0 82 #define MUX_ACLK_160_SEL_SCLKAPLL 0x1 83 #define MUX_ACLK_100_SEL_SCLKMPLL 0x0 84 #define MUX_ACLK_100_SEL_SCLKAPLL 0x1 85 #define MUX_ACLK_200_SEL_SCLKMPLL 0x0 86 #define MUX_ACLK_200_SEL_SCLKAPLL 0x1 87 #define MUX_VPLL_SEL_FINPLL 0x0 88 #define MUX_VPLL_SEL_FOUTVPLL 0x1 89 #define MUX_EPLL_SEL_FINPLL 0x0 90 #define MUX_EPLL_SEL_FOUTEPLL 0x1 91 #define MUX_ONENAND_1_SEL_MOUTONENAND 0x0 92 #define MUX_ONENAND_1_SEL_SCLKVPLL 0x1 93 #define CLK_SRC_TOP0_VAL ((MUX_ONENAND_SEL_ACLK_160 << 28) \ 94 | (MUX_ACLK_133_SEL_SCLKMPLL << 24) \ 95 | (MUX_ACLK_160_SEL_SCLKMPLL << 20) \ 96 | (MUX_ACLK_100_SEL_SCLKMPLL << 16) \ 97 | (MUX_ACLK_200_SEL_SCLKMPLL << 12) \ 98 | (MUX_VPLL_SEL_FOUTVPLL << 8) \ 99 | (MUX_EPLL_SEL_FOUTEPLL << 4) \ 100 | (MUX_ONENAND_1_SEL_MOUTONENAND << 0)) 101 102 /* CLK_DIV_TOP */ 103 #define ONENAND_RATIO 0x0 104 #define ACLK_133_RATIO 0x5 105 #define ACLK_160_RATIO 0x4 106 #define ACLK_100_RATIO 0x7 107 #define ACLK_200_RATIO 0x3 108 #define CLK_DIV_TOP_VAL ((ONENAND_RATIO << 16) \ 109 | (ACLK_133_RATIO << 12)\ 110 | (ACLK_160_RATIO << 8) \ 111 | (ACLK_100_RATIO << 4) \ 112 | (ACLK_200_RATIO << 0)) 113 114 /* CLK_DIV_LEFTBUS */ 115 #define GPL_RATIO 0x1 116 #define GDL_RATIO 0x3 117 #define CLK_DIV_LEFTBUS_VAL ((GPL_RATIO << 4) | (GDL_RATIO)) 118 119 /* CLK_DIV_RIGHTBUS */ 120 #define GPR_RATIO 0x1 121 #define GDR_RATIO 0x3 122 #define CLK_DIV_RIGHTBUS_VAL ((GPR_RATIO << 4) | (GDR_RATIO)) 123 124 /* CLK_SRS_FSYS: 6 = SCLKMPLL */ 125 #define SATA_SEL_SCLKMPLL 0 126 #define SATA_SEL_SCLKAPLL 1 127 128 #define MMC_SEL_XXTI 0 129 #define MMC_SEL_XUSBXTI 1 130 #define MMC_SEL_SCLK_HDMI24M 2 131 #define MMC_SEL_SCLK_USBPHY0 3 132 #define MMC_SEL_SCLK_USBPHY1 4 133 #define MMC_SEL_SCLK_HDMIPHY 5 134 #define MMC_SEL_SCLKMPLL 6 135 #define MMC_SEL_SCLKEPLL 7 136 #define MMC_SEL_SCLKVPLL 8 137 138 #define MMCC0_SEL MMC_SEL_SCLKMPLL 139 #define MMCC1_SEL MMC_SEL_SCLKMPLL 140 #define MMCC2_SEL MMC_SEL_SCLKMPLL 141 #define MMCC3_SEL MMC_SEL_SCLKMPLL 142 #define MMCC4_SEL MMC_SEL_SCLKMPLL 143 #define CLK_SRC_FSYS_VAL ((SATA_SEL_SCLKMPLL << 24) \ 144 | (MMCC4_SEL << 16) \ 145 | (MMCC3_SEL << 12) \ 146 | (MMCC2_SEL << 8) \ 147 | (MMCC1_SEL << 4) \ 148 | (MMCC0_SEL << 0)) 149 150 /* SCLK_MMC[0-4] = MOUTMMC[0-4]/(MMC[0-4]_RATIO + 1)/(MMC[0-4]_PRE_RATIO +1) */ 151 /* CLK_DIV_FSYS1: 800(MPLL) / (15 + 1) */ 152 #define MMC0_RATIO 0xF 153 #define MMC0_PRE_RATIO 0x0 154 #define MMC1_RATIO 0xF 155 #define MMC1_PRE_RATIO 0x0 156 #define CLK_DIV_FSYS1_VAL ((MMC1_PRE_RATIO << 24) \ 157 | (MMC1_RATIO << 16) \ 158 | (MMC0_PRE_RATIO << 8) \ 159 | (MMC0_RATIO << 0)) 160 161 /* CLK_DIV_FSYS2: 800(MPLL) / (15 + 1) */ 162 #define MMC2_RATIO 0xF 163 #define MMC2_PRE_RATIO 0x0 164 #define MMC3_RATIO 0xF 165 #define MMC3_PRE_RATIO 0x0 166 #define CLK_DIV_FSYS2_VAL ((MMC3_PRE_RATIO << 24) \ 167 | (MMC3_RATIO << 16) \ 168 | (MMC2_PRE_RATIO << 8) \ 169 | (MMC2_RATIO << 0)) 170 171 /* CLK_DIV_FSYS3: 800(MPLL) / (15 + 1) */ 172 #define MMC4_RATIO 0xF 173 #define MMC4_PRE_RATIO 0x0 174 #define CLK_DIV_FSYS3_VAL ((MMC4_PRE_RATIO << 8) \ 175 | (MMC4_RATIO << 0)) 176 177 /* CLK_SRC_PERIL0 */ 178 #define UART_SEL_XXTI 0 179 #define UART_SEL_XUSBXTI 1 180 #define UART_SEL_SCLK_HDMI24M 2 181 #define UART_SEL_SCLK_USBPHY0 3 182 #define UART_SEL_SCLK_USBPHY1 4 183 #define UART_SEL_SCLK_HDMIPHY 5 184 #define UART_SEL_SCLKMPLL 6 185 #define UART_SEL_SCLKEPLL 7 186 #define UART_SEL_SCLKVPLL 8 187 188 #define UART0_SEL UART_SEL_SCLKMPLL 189 #define UART1_SEL UART_SEL_SCLKMPLL 190 #define UART2_SEL UART_SEL_SCLKMPLL 191 #define UART3_SEL UART_SEL_SCLKMPLL 192 #define UART4_SEL UART_SEL_SCLKMPLL 193 #define UART5_SEL UART_SEL_SCLKMPLL 194 #define CLK_SRC_PERIL0_VAL ((UART5_SEL << 16) \ 195 | (UART4_SEL << 12) \ 196 | (UART3_SEL << 12) \ 197 | (UART2_SEL << 8) \ 198 | (UART1_SEL << 4) \ 199 | (UART0_SEL << 0)) 200 201 /* SCLK_UART[0-4] = MOUTUART[0-4] / (UART[0-4]_RATIO + 1) */ 202 /* CLK_DIV_PERIL0 */ 203 #define UART0_RATIO 7 204 #define UART1_RATIO 7 205 #define UART2_RATIO 7 206 #define UART3_RATIO 4 207 #define UART4_RATIO 7 208 #define UART5_RATIO 7 209 #define CLK_DIV_PERIL0_VAL ((UART5_RATIO << 16) \ 210 | (UART4_RATIO << 12) \ 211 | (UART3_RATIO << 12) \ 212 | (UART2_RATIO << 8) \ 213 | (UART1_RATIO << 4) \ 214 | (UART0_RATIO << 0)) 215 216 /* CLK_DIV_PERIL3 */ 217 #define SLIMBUS_RATIO 0x0 218 #define PWM_RATIO 0x8 219 #define CLK_DIV_PERIL3_VAL ((SLIMBUS_RATIO << 4) \ 220 | (PWM_RATIO << 0)) 221 222 /* Required period to generate a stable clock output */ 223 /* PLL_LOCK_TIME */ 224 #define PLL_LOCKTIME 0x1C20 225 226 /* PLL Values */ 227 #define DISABLE 0 228 #define ENABLE 1 229 #define SET_PLL(mdiv, pdiv, sdiv) ((ENABLE << 31)\ 230 | (mdiv << 16) \ 231 | (pdiv << 8) \ 232 | (sdiv << 0)) 233 234 /* APLL_CON0: 800MHz */ 235 #define APLL_MDIV 0xC8 236 #define APLL_PDIV 0x6 237 #define APLL_SDIV 0x1 238 #define APLL_CON0_VAL SET_PLL(APLL_MDIV, APLL_PDIV, APLL_SDIV) 239 240 /* APLL_CON1 */ 241 #define APLL_AFC_ENB 0x1 242 #define APLL_AFC 0x1C 243 #define APLL_CON1_VAL ((APLL_AFC_ENB << 31) | (APLL_AFC << 0)) 244 245 /* MPLL_CON0: 800MHz */ 246 #define MPLL_MDIV 0xC8 247 #define MPLL_PDIV 0x6 248 #define MPLL_SDIV 0x1 249 #define MPLL_CON0_VAL SET_PLL(MPLL_MDIV, MPLL_PDIV, MPLL_SDIV) 250 251 /* MPLL_CON1 */ 252 #define MPLL_AFC_ENB 0x1 253 #define MPLL_AFC 0x1C 254 #define MPLL_CON1_VAL ((MPLL_AFC_ENB << 31) | (MPLL_AFC << 0)) 255 256 /* EPLL_CON0: 96MHz */ 257 #define EPLL_MDIV 0x30 258 #define EPLL_PDIV 0x3 259 #define EPLL_SDIV 0x2 260 #define EPLL_CON0_VAL SET_PLL(EPLL_MDIV, EPLL_PDIV, EPLL_SDIV) 261 262 /* EPLL_CON1 */ 263 #define EPLL_K 0x0 264 #define EPLL_CON1_VAL (EPLL_K >> 0) 265 266 /* VPLL_CON0: 108MHz */ 267 #define VPLL_MDIV 0x35 268 #define VPLL_PDIV 0x3 269 #define VPLL_SDIV 0x2 270 #define VPLL_CON0_VAL SET_PLL(VPLL_MDIV, VPLL_PDIV, VPLL_SDIV) 271 272 /* VPLL_CON1 */ 273 #define VPLL_SSCG_EN DISABLE 274 #define VPLL_SEL_PF_DN_SPREAD 0x0 275 #define VPLL_MRR 0x11 276 #define VPLL_MFR 0x0 277 #define VPLL_K 0x400 278 #define VPLL_CON1_VAL ((VPLL_SSCG_EN << 31)\ 279 | (VPLL_SEL_PF_DN_SPREAD << 29) \ 280 | (VPLL_MRR << 24) \ 281 | (VPLL_MFR << 16) \ 282 | (VPLL_K << 0)) 283 284 /* CLOCK GATE */ 285 #define CLK_DIS 0x0 286 #define CLK_EN 0x1 287 288 #define BIT_CAM_CLK_PIXELASYNCM1 18 289 #define BIT_CAM_CLK_PIXELASYNCM0 17 290 #define BIT_CAM_CLK_PPMUCAMIF 16 291 #define BIT_CAM_CLK_QEFIMC3 15 292 #define BIT_CAM_CLK_QEFIMC2 14 293 #define BIT_CAM_CLK_QEFIMC1 13 294 #define BIT_CAM_CLK_QEFIMC0 12 295 #define BIT_CAM_CLK_SMMUJPEG 11 296 #define BIT_CAM_CLK_SMMUFIMC3 10 297 #define BIT_CAM_CLK_SMMUFIMC2 9 298 #define BIT_CAM_CLK_SMMUFIMC1 8 299 #define BIT_CAM_CLK_SMMUFIMC0 7 300 #define BIT_CAM_CLK_JPEG 6 301 #define BIT_CAM_CLK_CSIS1 5 302 #define BIT_CAM_CLK_CSIS0 4 303 #define BIT_CAM_CLK_FIMC3 3 304 #define BIT_CAM_CLK_FIMC2 2 305 #define BIT_CAM_CLK_FIMC1 1 306 #define BIT_CAM_CLK_FIMC0 0 307 #define CLK_GATE_IP_CAM_ALL_EN ((CLK_EN << BIT_CAM_CLK_PIXELASYNCM1)\ 308 | (CLK_EN << BIT_CAM_CLK_PIXELASYNCM0)\ 309 | (CLK_EN << BIT_CAM_CLK_PPMUCAMIF)\ 310 | (CLK_EN << BIT_CAM_CLK_QEFIMC3)\ 311 | (CLK_EN << BIT_CAM_CLK_QEFIMC2)\ 312 | (CLK_EN << BIT_CAM_CLK_QEFIMC1)\ 313 | (CLK_EN << BIT_CAM_CLK_QEFIMC0)\ 314 | (CLK_EN << BIT_CAM_CLK_SMMUJPEG)\ 315 | (CLK_EN << BIT_CAM_CLK_SMMUFIMC3)\ 316 | (CLK_EN << BIT_CAM_CLK_SMMUFIMC2)\ 317 | (CLK_EN << BIT_CAM_CLK_SMMUFIMC1)\ 318 | (CLK_EN << BIT_CAM_CLK_SMMUFIMC0)\ 319 | (CLK_EN << BIT_CAM_CLK_JPEG)\ 320 | (CLK_EN << BIT_CAM_CLK_CSIS1)\ 321 | (CLK_EN << BIT_CAM_CLK_CSIS0)\ 322 | (CLK_EN << BIT_CAM_CLK_FIMC3)\ 323 | (CLK_EN << BIT_CAM_CLK_FIMC2)\ 324 | (CLK_EN << BIT_CAM_CLK_FIMC1)\ 325 | (CLK_EN << BIT_CAM_CLK_FIMC0)) 326 #define CLK_GATE_IP_CAM_ALL_DIS ~CLK_GATE_IP_CAM_ALL_EN 327 328 #define BIT_VP_CLK_PPMUTV 5 329 #define BIT_VP_CLK_SMMUTV 4 330 #define BIT_VP_CLK_HDMI 3 331 #define BIT_VP_CLK_TVENC 2 332 #define BIT_VP_CLK_MIXER 1 333 #define BIT_VP_CLK_VP 0 334 #define CLK_GATE_IP_VP_ALL_EN ((CLK_EN << BIT_VP_CLK_PPMUTV)\ 335 | (CLK_EN << BIT_VP_CLK_SMMUTV)\ 336 | (CLK_EN << BIT_VP_CLK_HDMI)\ 337 | (CLK_EN << BIT_VP_CLK_TVENC)\ 338 | (CLK_EN << BIT_VP_CLK_MIXER)\ 339 | (CLK_EN << BIT_VP_CLK_VP)) 340 #define CLK_GATE_IP_VP_ALL_DIS ~CLK_GATE_IP_VP_ALL_EN 341 342 #define BIT_MFC_CLK_PPMUMFC_R 4 343 #define BIT_MFC_CLK_PPMUMFC_L 3 344 #define BIT_MFC_CLK_SMMUMFC_R 2 345 #define BIT_MFC_CLK_SMMUMFC_L 1 346 #define BIT_MFC_CLK_MFC 0 347 #define CLK_GATE_IP_MFC_ALL_EN ((CLK_EN << BIT_MFC_CLK_PPMUMFC_R)\ 348 | (CLK_EN << BIT_MFC_CLK_PPMUMFC_L)\ 349 | (CLK_EN << BIT_MFC_CLK_SMMUMFC_R)\ 350 | (CLK_EN << BIT_MFC_CLK_SMMUMFC_L)\ 351 | (CLK_EN << BIT_MFC_CLK_MFC)) 352 #define CLK_GATE_IP_MFC_ALL_DIS ~CLK_GATE_IP_MFC_ALL_EN 353 354 #define BIT_G3D_CLK_QEG3D 2 355 #define BIT_G3D_CLK_PPMUG3D 1 356 #define BIT_G3D_CLK_G3D 0 357 #define CLK_GATE_IP_G3D_ALL_EN ((CLK_EN << BIT_G3D_CLK_QEG3D)\ 358 | (CLK_EN << BIT_G3D_CLK_PPMUG3D)\ 359 | (CLK_EN << BIT_G3D_CLK_G3D)) 360 #define CLK_GATE_IP_G3D_ALL_DIS ~CLK_GATE_IP_G3D_ALL_EN 361 362 #define BIT_IMAGE_CLK_PPMUIMAGE 9 363 #define BIT_IMAGE_CLK_QEMDMA 8 364 #define BIT_IMAGE_CLK_QEROTATOR 7 365 #define BIT_IMAGE_CLK_QEG2D 6 366 #define BIT_IMAGE_CLK_SMMUMDMA 5 367 #define BIT_IMAGE_CLK_SMMUROTATOR 4 368 #define BIT_IMAGE_CLK_SMMUG2D 3 369 #define BIT_IMAGE_CLK_MDMA 2 370 #define BIT_IMAGE_CLK_ROTATOR 1 371 #define BIT_IMAGE_CLK_G2D 0 372 #define CLK_GATE_IP_IMAGE_ALL_EN ((CLK_EN << BIT_IMAGE_CLK_PPMUIMAGE)\ 373 | (CLK_EN << BIT_IMAGE_CLK_QEMDMA)\ 374 | (CLK_EN << BIT_IMAGE_CLK_QEROTATOR)\ 375 | (CLK_EN << BIT_IMAGE_CLK_QEG2D)\ 376 | (CLK_EN << BIT_IMAGE_CLK_SMMUMDMA)\ 377 | (CLK_EN << BIT_IMAGE_CLK_SMMUROTATOR)\ 378 | (CLK_EN << BIT_IMAGE_CLK_SMMUG2D)\ 379 | (CLK_EN << BIT_IMAGE_CLK_MDMA)\ 380 | (CLK_EN << BIT_IMAGE_CLK_ROTATOR)\ 381 | (CLK_EN << BIT_IMAGE_CLK_G2D)) 382 #define CLK_GATE_IP_IMAGE_ALL_DIS ~CLK_GATE_IP_IMAGE_ALL_EN 383 384 #define BIT_LCD0_CLK_PPMULCD0 5 385 #define BIT_LCD0_CLK_SMMUFIMD0 4 386 #define BIT_LCD0_CLK_DSIM0 3 387 #define BIT_LCD0_CLK_MDNIE0 2 388 #define BIT_LCD0_CLK_MIE0 1 389 #define BIT_LCD0_CLK_FIMD0 0 390 #define CLK_GATE_IP_LCD0_ALL_EN ((CLK_EN << BIT_LCD0_CLK_PPMULCD0)\ 391 | (CLK_EN << BIT_LCD0_CLK_SMMUFIMD0)\ 392 | (CLK_EN << BIT_LCD0_CLK_DSIM0)\ 393 | (CLK_EN << BIT_LCD0_CLK_MDNIE0)\ 394 | (CLK_EN << BIT_LCD0_CLK_MIE0)\ 395 | (CLK_EN << BIT_LCD0_CLK_FIMD0)) 396 #define CLK_GATE_IP_LCD0_ALL_DIS ~CLK_GATE_IP_LCD0_ALL_EN 397 398 #define BIT_LCD1_CLK_PPMULCD1 5 399 #define BIT_LCD1_CLK_SMMUFIMD1 4 400 #define BIT_LCD1_CLK_DSIM1 3 401 #define BIT_LCD1_CLK_MDNIE1 2 402 #define BIT_LCD1_CLK_MIE1 1 403 #define BIT_LCD1_CLK_FIMD1 0 404 #define CLK_GATE_IP_LCD1_ALL_EN ((CLK_EN << BIT_LCD1_CLK_PPMULCD1)\ 405 | (CLK_EN << BIT_LCD1_CLK_SMMUFIMD1)\ 406 | (CLK_EN << BIT_LCD1_CLK_DSIM1)\ 407 | (CLK_EN << BIT_LCD1_CLK_MDNIE1)\ 408 | (CLK_EN << BIT_LCD1_CLK_MIE1)\ 409 | (CLK_EN << BIT_LCD1_CLK_FIMD1)) 410 #define CLK_GATE_IP_LCD1_ALL_DIS ~CLK_GATE_IP_LCD1_ALL_EN 411 412 #define BIT_FSYS_CLK_SMMUPCIE 18 413 #define BIT_FSYS_CLK_PPMUFILE 17 414 #define BIT_FSYS_CLK_NFCON 16 415 #define BIT_FSYS_CLK_ONENAND 15 416 #define BIT_FSYS_CLK_PCIE 14 417 #define BIT_FSYS_CLK_USBDEVICE 13 418 #define BIT_FSYS_CLK_USBHOST 12 419 #define BIT_FSYS_CLK_SROMC 11 420 #define BIT_FSYS_CLK_SATA 10 421 #define BIT_FSYS_CLK_SDMMC4 9 422 #define BIT_FSYS_CLK_SDMMC3 8 423 #define BIT_FSYS_CLK_SDMMC2 7 424 #define BIT_FSYS_CLK_SDMMC1 6 425 #define BIT_FSYS_CLK_SDMMC0 5 426 #define BIT_FSYS_CLK_TSI 4 427 #define BIT_FSYS_CLK_SATAPHY 3 428 #define BIT_FSYS_CLK_PCIEPHY 2 429 #define BIT_FSYS_CLK_PDMA1 1 430 #define BIT_FSYS_CLK_PDMA0 0 431 #define CLK_GATE_IP_FSYS_ALL_EN ((CLK_EN << BIT_FSYS_CLK_SMMUPCIE)\ 432 | (CLK_EN << BIT_FSYS_CLK_PPMUFILE)\ 433 | (CLK_EN << BIT_FSYS_CLK_NFCON)\ 434 | (CLK_EN << BIT_FSYS_CLK_ONENAND)\ 435 | (CLK_EN << BIT_FSYS_CLK_PCIE)\ 436 | (CLK_EN << BIT_FSYS_CLK_USBDEVICE)\ 437 | (CLK_EN << BIT_FSYS_CLK_USBHOST)\ 438 | (CLK_EN << BIT_FSYS_CLK_SROMC)\ 439 | (CLK_EN << BIT_FSYS_CLK_SATA)\ 440 | (CLK_EN << BIT_FSYS_CLK_SDMMC4)\ 441 | (CLK_EN << BIT_FSYS_CLK_SDMMC3)\ 442 | (CLK_EN << BIT_FSYS_CLK_SDMMC2)\ 443 | (CLK_EN << BIT_FSYS_CLK_SDMMC1)\ 444 | (CLK_EN << BIT_FSYS_CLK_SDMMC0)\ 445 | (CLK_EN << BIT_FSYS_CLK_TSI)\ 446 | (CLK_EN << BIT_FSYS_CLK_SATAPHY)\ 447 | (CLK_EN << BIT_FSYS_CLK_PCIEPHY)\ 448 | (CLK_EN << BIT_FSYS_CLK_PDMA1)\ 449 | (CLK_EN << BIT_FSYS_CLK_PDMA0)) 450 #define CLK_GATE_IP_FSYS_ALL_DIS ~CLK_GATE_IP_FSYS_ALL_EN 451 452 #define BIT_GPS_CLK_SMMUGPS 1 453 #define BIT_GPS_CLK_GPS 0 454 #define CLK_GATE_IP_GPS_ALL_EN ((CLK_EN << BIT_GPS_CLK_SMMUGPS)\ 455 | (CLK_EN << BIT_GPS_CLK_GPS)) 456 #define CLK_GATE_IP_GPS_ALL_DIS ~CLK_GATE_IP_GPS_ALL_EN 457 458 #define BIT_PERIL_CLK_MODEMIF 28 459 #define BIT_PERIL_CLK_AC97 27 460 #define BIT_PERIL_CLK_SPDIF 26 461 #define BIT_PERIL_CLK_SLIMBUS 25 462 #define BIT_PERIL_CLK_PWM 24 463 #define BIT_PERIL_CLK_PCM2 23 464 #define BIT_PERIL_CLK_PCM1 22 465 #define BIT_PERIL_CLK_I2S2 21 466 #define BIT_PERIL_CLK_I2S1 20 467 #define BIT_PERIL_CLK_RESERVED0 19 468 #define BIT_PERIL_CLK_SPI2 18 469 #define BIT_PERIL_CLK_SPI1 17 470 #define BIT_PERIL_CLK_SPI0 16 471 #define BIT_PERIL_CLK_TSADC 15 472 #define BIT_PERIL_CLK_I2CHDMI 14 473 #define BIT_PERIL_CLK_I2C7 13 474 #define BIT_PERIL_CLK_I2C6 12 475 #define BIT_PERIL_CLK_I2C5 11 476 #define BIT_PERIL_CLK_I2C4 10 477 #define BIT_PERIL_CLK_I2C3 9 478 #define BIT_PERIL_CLK_I2C2 8 479 #define BIT_PERIL_CLK_I2C1 7 480 #define BIT_PERIL_CLK_I2C0 6 481 #define BIT_PERIL_CLK_RESERVED1 5 482 #define BIT_PERIL_CLK_UART4 4 483 #define BIT_PERIL_CLK_UART3 3 484 #define BIT_PERIL_CLK_UART2 2 485 #define BIT_PERIL_CLK_UART1 1 486 #define BIT_PERIL_CLK_UART0 0 487 #define CLK_GATE_IP_PERIL_ALL_EN ((CLK_EN << BIT_PERIL_CLK_MODEMIF)\ 488 | (CLK_EN << BIT_PERIL_CLK_AC97)\ 489 | (CLK_EN << BIT_PERIL_CLK_SPDIF)\ 490 | (CLK_EN << BIT_PERIL_CLK_SLIMBUS)\ 491 | (CLK_EN << BIT_PERIL_CLK_PWM)\ 492 | (CLK_EN << BIT_PERIL_CLK_PCM2)\ 493 | (CLK_EN << BIT_PERIL_CLK_PCM1)\ 494 | (CLK_EN << BIT_PERIL_CLK_I2S2)\ 495 | (CLK_EN << BIT_PERIL_CLK_I2S1)\ 496 | (CLK_EN << BIT_PERIL_CLK_RESERVED0)\ 497 | (CLK_EN << BIT_PERIL_CLK_SPI2)\ 498 | (CLK_EN << BIT_PERIL_CLK_SPI1)\ 499 | (CLK_EN << BIT_PERIL_CLK_SPI0)\ 500 | (CLK_EN << BIT_PERIL_CLK_TSADC)\ 501 | (CLK_EN << BIT_PERIL_CLK_I2CHDMI)\ 502 | (CLK_EN << BIT_PERIL_CLK_I2C7)\ 503 | (CLK_EN << BIT_PERIL_CLK_I2C6)\ 504 | (CLK_EN << BIT_PERIL_CLK_I2C5)\ 505 | (CLK_EN << BIT_PERIL_CLK_I2C4)\ 506 | (CLK_EN << BIT_PERIL_CLK_I2C3)\ 507 | (CLK_EN << BIT_PERIL_CLK_I2C2)\ 508 | (CLK_EN << BIT_PERIL_CLK_I2C1)\ 509 | (CLK_EN << BIT_PERIL_CLK_I2C0)\ 510 | (CLK_EN << BIT_PERIL_CLK_RESERVED1)\ 511 | (CLK_EN << BIT_PERIL_CLK_UART4)\ 512 | (CLK_EN << BIT_PERIL_CLK_UART3)\ 513 | (CLK_EN << BIT_PERIL_CLK_UART2)\ 514 | (CLK_EN << BIT_PERIL_CLK_UART1)\ 515 | (CLK_EN << BIT_PERIL_CLK_UART0)) 516 #define CLK_GATE_IP_PERIL_ALL_DIS ~CLK_GATE_IP_PERIL_ALL_EN 517 518 #define BIT_PERIR_CLK_TMU_APBIF 17 519 #define BIT_PERIR_CLK_KEYIF 16 520 #define BIT_PERIR_CLK_RTC 15 521 #define BIT_PERIR_CLK_WDT 14 522 #define BIT_PERIR_CLK_MCT 13 523 #define BIT_PERIR_CLK_SECKEY 12 524 #define BIT_PERIR_CLK_HDMI_CEC 11 525 #define BIT_PERIR_CLK_TZPC5 10 526 #define BIT_PERIR_CLK_TZPC4 9 527 #define BIT_PERIR_CLK_TZPC3 8 528 #define BIT_PERIR_CLK_TZPC2 7 529 #define BIT_PERIR_CLK_TZPC1 6 530 #define BIT_PERIR_CLK_TZPC0 5 531 #define BIT_PERIR_CLK_CMU_DMCPART 4 532 #define BIT_PERIR_CLK_RESERVED 3 533 #define BIT_PERIR_CLK_CMU_APBIF 2 534 #define BIT_PERIR_CLK_SYSREG 1 535 #define BIT_PERIR_CLK_CHIP_ID 0 536 #define CLK_GATE_IP_PERIR_ALL_EN ((CLK_EN << BIT_PERIR_CLK_TMU_APBIF)\ 537 | (CLK_EN << BIT_PERIR_CLK_KEYIF)\ 538 | (CLK_EN << BIT_PERIR_CLK_RTC)\ 539 | (CLK_EN << BIT_PERIR_CLK_WDT)\ 540 | (CLK_EN << BIT_PERIR_CLK_MCT)\ 541 | (CLK_EN << BIT_PERIR_CLK_SECKEY)\ 542 | (CLK_EN << BIT_PERIR_CLK_HDMI_CEC)\ 543 | (CLK_EN << BIT_PERIR_CLK_TZPC5)\ 544 | (CLK_EN << BIT_PERIR_CLK_TZPC4)\ 545 | (CLK_EN << BIT_PERIR_CLK_TZPC3)\ 546 | (CLK_EN << BIT_PERIR_CLK_TZPC2)\ 547 | (CLK_EN << BIT_PERIR_CLK_TZPC1)\ 548 | (CLK_EN << BIT_PERIR_CLK_TZPC0)\ 549 | (CLK_EN << BIT_PERIR_CLK_CMU_DMCPART)\ 550 | (CLK_EN << BIT_PERIR_CLK_RESERVED)\ 551 | (CLK_EN << BIT_PERIR_CLK_CMU_APBIF)\ 552 | (CLK_EN << BIT_PERIR_CLK_SYSREG)\ 553 | (CLK_EN << BIT_PERIR_CLK_CHIP_ID)) 554 #define CLK_GATE_IP_PERIR_ALL_DIS ~CLK_GATE_IP_PERIR_ALL_EN 555 556 #define BIT_BLOCK_CLK_GPS 7 557 #define BIT_BLOCK_CLK_RESERVED 6 558 #define BIT_BLOCK_CLK_LCD1 5 559 #define BIT_BLOCK_CLK_LCD0 4 560 #define BIT_BLOCK_CLK_G3D 3 561 #define BIT_BLOCK_CLK_MFC 2 562 #define BIT_BLOCK_CLK_TV 1 563 #define BIT_BLOCK_CLK_CAM 0 564 #define CLK_GATE_BLOCK_ALL_EN ((CLK_EN << BIT_BLOCK_CLK_GPS)\ 565 | (CLK_EN << BIT_BLOCK_CLK_RESERVED)\ 566 | (CLK_EN << BIT_BLOCK_CLK_LCD1)\ 567 | (CLK_EN << BIT_BLOCK_CLK_LCD0)\ 568 | (CLK_EN << BIT_BLOCK_CLK_G3D)\ 569 | (CLK_EN << BIT_BLOCK_CLK_MFC)\ 570 | (CLK_EN << BIT_BLOCK_CLK_TV)\ 571 | (CLK_EN << BIT_BLOCK_CLK_CAM)) 572 #define CLK_GATE_BLOCK_ALL_DIS ~CLK_GATE_BLOCK_ALL_EN 573 574 /* 575 * GATE CAM : All block 576 * GATE VP : All block 577 * GATE MFC : All block 578 * GATE G3D : All block 579 * GATE IMAGE : All block 580 * GATE LCD0 : All block 581 * GATE LCD1 : All block 582 * GATE FSYS : Enable - PDMA0,1, SDMMC0,2, USBHOST, USBDEVICE, PPMUFILE 583 * GATE GPS : All block 584 * GATE PERI Left : All Enable, Block - SLIMBUS, SPDIF, AC97 585 * GATE PERI Right : All Enable, Block - KEYIF 586 * GATE Block : All block 587 */ 588 #define CLK_GATE_IP_CAM_VAL CLK_GATE_IP_CAM_ALL_DIS 589 #define CLK_GATE_IP_VP_VAL CLK_GATE_IP_VP_ALL_DIS 590 #define CLK_GATE_IP_MFC_VAL CLK_GATE_IP_MFC_ALL_DIS 591 #define CLK_GATE_IP_G3D_VAL CLK_GATE_IP_G3D_ALL_DIS 592 #define CLK_GATE_IP_IMAGE_VAL CLK_GATE_IP_IMAGE_ALL_DIS 593 #define CLK_GATE_IP_LCD0_VAL CLK_GATE_IP_LCD0_ALL_DIS 594 #define CLK_GATE_IP_LCD1_VAL CLK_GATE_IP_LCD1_ALL_DIS 595 #define CLK_GATE_IP_FSYS_VAL (CLK_GATE_IP_FSYS_ALL_DIS \ 596 | (CLK_EN << BIT_FSYS_CLK_PPMUFILE)\ 597 | (CLK_EN << BIT_FSYS_CLK_USBDEVICE)\ 598 | (CLK_EN << BIT_FSYS_CLK_USBHOST)\ 599 | (CLK_EN << BIT_FSYS_CLK_SROMC)\ 600 | (CLK_EN << BIT_FSYS_CLK_SDMMC2)\ 601 | (CLK_EN << BIT_FSYS_CLK_SDMMC0)\ 602 | (CLK_EN << BIT_FSYS_CLK_PDMA1)\ 603 | (CLK_EN << BIT_FSYS_CLK_PDMA0)) 604 #define CLK_GATE_IP_GPS_VAL CLK_GATE_IP_GPS_ALL_DIS 605 #define CLK_GATE_IP_PERIL_VAL (CLK_GATE_IP_PERIL_ALL_DIS \ 606 | ~((CLK_EN << BIT_PERIL_CLK_AC97)\ 607 | (CLK_EN << BIT_PERIL_CLK_SPDIF)\ 608 | (CLK_EN << BIT_PERIL_CLK_I2C2)\ 609 | (CLK_EN << BIT_PERIL_CLK_SLIMBUS))) 610 #define CLK_GATE_IP_PERIR_VAL (CLK_GATE_IP_PERIR_ALL_DIS \ 611 | ~((CLK_EN << BIT_PERIR_CLK_KEYIF))) 612 #define CLK_GATE_BLOCK_VAL CLK_GATE_BLOCK_ALL_DIS 613 614 /* PS_HOLD: Data Hight, Output En */ 615 #define BIT_DAT 8 616 #define BIT_EN 9 617 #define EXYNOS4_PS_HOLD_CON_VAL (0x1 << BIT_DAT | 0x1 << BIT_EN) 618 619 #endif 620