1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * mux.c 4 * 5 * Copyright (C) 2013 Lothar Felten <lothar.felten (at) gmail.com> 6 */ 7 8 #include <common.h> 9 #include <asm/arch/sys_proto.h> 10 #include <asm/arch/hardware.h> 11 #include <asm/arch/mux.h> 12 #include <asm/io.h> 13 #include "board.h" 14 15 /* UART0 pins E15(rx),E16(tx) [E17(rts),E18(cts)] */ 16 static struct module_pin_mux uart0_pin_mux[] = { 17 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */ 18 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */ 19 {-1}, 20 }; 21 22 /* unused: UART1 pins D15(tx),D16(rx),D17(cts),D18(rts) */ 23 24 /* I2C pins C16(scl)/C17(sda) */ 25 static struct module_pin_mux i2c0_pin_mux[] = { 26 {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | 27 PULLUDEN | SLEWCTRL)}, /* I2C0_DATA */ 28 {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | 29 PULLUDEN | SLEWCTRL)}, /* I2C0_SCLK */ 30 {-1}, 31 }; 32 33 /* MMC0 pins */ 34 static struct module_pin_mux mmc0_pin_mux[] = { 35 {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */ 36 {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */ 37 {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */ 38 {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */ 39 {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */ 40 {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */ 41 {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */ 42 {-1}, 43 }; 44 45 /* MII pins */ 46 static struct module_pin_mux mii1_pin_mux[] = { 47 {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */ 48 {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */ 49 {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */ 50 {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */ 51 {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */ 52 {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */ 53 {OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */ 54 {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */ 55 {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */ 56 {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */ 57 {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */ 58 {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */ 59 {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */ 60 {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */ 61 {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ 62 {-1}, 63 }; 64 65 /* NAND pins */ 66 static struct module_pin_mux nand_pin_mux[] = { 67 {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */ 68 {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */ 69 {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */ 70 {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */ 71 {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */ 72 {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */ 73 {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */ 74 {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */ 75 {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */ 76 {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */ 77 {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */ 78 {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */ 79 {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */ 80 {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */ 81 {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */ 82 {-1}, 83 }; 84 85 void enable_uart0_pin_mux(void) 86 { 87 configure_module_pin_mux(uart0_pin_mux); 88 } 89 90 void enable_board_pin_mux() 91 { 92 configure_module_pin_mux(i2c0_pin_mux); 93 configure_module_pin_mux(uart0_pin_mux); 94 configure_module_pin_mux(mii1_pin_mux); 95 configure_module_pin_mux(mmc0_pin_mux); 96 configure_module_pin_mux(nand_pin_mux); 97 } 98
