1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2013 Freescale Semiconductor, Inc. 4 * 5 * Author: Fabio Estevam <fabio.estevam (at) freescale.com> 6 */ 7 8 #include <asm/arch/clock.h> 9 #include <asm/arch/imx-regs.h> 10 #include <asm/arch/iomux.h> 11 #include <malloc.h> 12 #include <asm/arch/mx6-pins.h> 13 #include <linux/errno.h> 14 #include <asm/gpio.h> 15 #include <asm/mach-imx/iomux-v3.h> 16 #include <asm/mach-imx/sata.h> 17 #include <mmc.h> 18 #include <fsl_esdhc.h> 19 #include <asm/arch/crm_regs.h> 20 #include <asm/io.h> 21 #include <asm/arch/sys_proto.h> 22 #include <micrel.h> 23 #include <miiphy.h> 24 #include <netdev.h> 25 26 DECLARE_GLOBAL_DATA_PTR; 27 28 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 29 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ 30 PAD_CTL_SRE_FAST | PAD_CTL_HYS) 31 32 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 33 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) 34 35 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ 36 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ 37 PAD_CTL_SRE_FAST | PAD_CTL_HYS) 38 39 #define WDT_EN IMX_GPIO_NR(5, 4) 40 #define WDT_TRG IMX_GPIO_NR(3, 19) 41 42 int dram_init(void) 43 { 44 gd->ram_size = imx_ddr_size(); 45 46 return 0; 47 } 48 49 static iomux_v3_cfg_t const uart2_pads[] = { 50 IOMUX_PADS(PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), 51 IOMUX_PADS(PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), 52 }; 53 54 static iomux_v3_cfg_t const usdhc3_pads[] = { 55 IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 56 IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 57 IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 58 IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 59 IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 60 IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 61 }; 62 63 static iomux_v3_cfg_t const wdog_pads[] = { 64 IOMUX_PADS(PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL)), 65 IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19), 66 }; 67 68 int mx6_rgmii_rework(struct phy_device *phydev) 69 { 70 /* 71 * Bug: Apparently uDoo does not works with Gigabit switches... 72 * Limiting speed to 10/100Mbps, and setting master mode, seems to 73 * be the only way to have a successfull PHY auto negotiation. 74 * How to fix: Understand why Linux kernel do not have this issue. 75 */ 76 phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, 0x1c00); 77 78 /* control data pad skew - devaddr = 0x02, register = 0x04 */ 79 ksz9031_phy_extended_write(phydev, 0x02, 80 MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW, 81 MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000); 82 /* rx data pad skew - devaddr = 0x02, register = 0x05 */ 83 ksz9031_phy_extended_write(phydev, 0x02, 84 MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, 85 MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000); 86 /* tx data pad skew - devaddr = 0x02, register = 0x05 */ 87 ksz9031_phy_extended_write(phydev, 0x02, 88 MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, 89 MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000); 90 /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */ 91 ksz9031_phy_extended_write(phydev, 0x02, 92 MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, 93 MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF); 94 return 0; 95 } 96 97 static iomux_v3_cfg_t const enet_pads1[] = { 98 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)), 99 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)), 100 IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), 101 IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 102 IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 103 IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 104 IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 105 IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)), 106 IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)), 107 IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), 108 /* RGMII reset */ 109 IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL)), 110 /* Ethernet power supply */ 111 IOMUX_PADS(PAD_EIM_EB3__GPIO2_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)), 112 /* pin 32 - 1 - (MODE0) all */ 113 IOMUX_PADS(PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)), 114 /* pin 31 - 1 - (MODE1) all */ 115 IOMUX_PADS(PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL)), 116 /* pin 28 - 1 - (MODE2) all */ 117 IOMUX_PADS(PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)), 118 /* pin 27 - 1 - (MODE3) all */ 119 IOMUX_PADS(PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)), 120 /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */ 121 IOMUX_PADS(PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL)), 122 }; 123 124 static iomux_v3_cfg_t const enet_pads2[] = { 125 IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 126 IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 127 IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 128 IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 129 IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)), 130 }; 131 132 static void setup_iomux_enet(void) 133 { 134 SETUP_IOMUX_PADS(enet_pads1); 135 udelay(20); 136 gpio_direction_output(IMX_GPIO_NR(2, 31), 1); /* Power supply on */ 137 138 gpio_direction_output(IMX_GPIO_NR(3, 23), 0); /* assert PHY rst */ 139 140 gpio_direction_output(IMX_GPIO_NR(6, 24), 1); 141 gpio_direction_output(IMX_GPIO_NR(6, 25), 1); 142 gpio_direction_output(IMX_GPIO_NR(6, 27), 1); 143 gpio_direction_output(IMX_GPIO_NR(6, 28), 1); 144 gpio_direction_output(IMX_GPIO_NR(6, 29), 1); 145 udelay(1000); 146 147 gpio_set_value(IMX_GPIO_NR(3, 23), 1); /* deassert PHY rst */ 148 149 /* Need 100ms delay to exit from reset. */ 150 udelay(1000 * 100); 151 152 gpio_free(IMX_GPIO_NR(6, 24)); 153 gpio_free(IMX_GPIO_NR(6, 25)); 154 gpio_free(IMX_GPIO_NR(6, 27)); 155 gpio_free(IMX_GPIO_NR(6, 28)); 156 gpio_free(IMX_GPIO_NR(6, 29)); 157 158 SETUP_IOMUX_PADS(enet_pads2); 159 } 160 161 static void setup_iomux_uart(void) 162 { 163 SETUP_IOMUX_PADS(uart2_pads); 164 } 165 166 static void setup_iomux_wdog(void) 167 { 168 SETUP_IOMUX_PADS(wdog_pads); 169 gpio_direction_output(WDT_TRG, 0); 170 gpio_direction_output(WDT_EN, 1); 171 gpio_direction_input(WDT_TRG); 172 } 173 174 static struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR }; 175 176 int board_mmc_getcd(struct mmc *mmc) 177 { 178 return 1; /* Always present */ 179 } 180 181 int board_eth_init(bd_t *bis) 182 { 183 uint32_t base = IMX_FEC_BASE; 184 struct mii_dev *bus = NULL; 185 struct phy_device *phydev = NULL; 186 int ret; 187 188 setup_iomux_enet(); 189 190 #ifdef CONFIG_FEC_MXC 191 bus = fec_get_miibus(base, -1); 192 if (!bus) 193 return -EINVAL; 194 /* scan phy 4,5,6,7 */ 195 phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII); 196 197 if (!phydev) { 198 ret = -EINVAL; 199 goto free_bus; 200 } 201 printf("using phy at %d\n", phydev->addr); 202 ret = fec_probe(bis, -1, base, bus, phydev); 203 if (ret) 204 goto free_phydev; 205 #endif 206 return 0; 207 208 free_phydev: 209 free(phydev); 210 free_bus: 211 free(bus); 212 return ret; 213 } 214 215 int board_mmc_init(bd_t *bis) 216 { 217 SETUP_IOMUX_PADS(usdhc3_pads); 218 usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 219 usdhc_cfg.max_bus_width = 4; 220 221 return fsl_esdhc_initialize(bis, &usdhc_cfg); 222 } 223 224 int board_early_init_f(void) 225 { 226 setup_iomux_wdog(); 227 setup_iomux_uart(); 228 229 return 0; 230 } 231 232 int board_phy_config(struct phy_device *phydev) 233 { 234 mx6_rgmii_rework(phydev); 235 if (phydev->drv->config) 236 phydev->drv->config(phydev); 237 238 return 0; 239 } 240 241 int board_init(void) 242 { 243 /* address of boot parameters */ 244 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 245 246 #ifdef CONFIG_SATA 247 setup_sata(); 248 #endif 249 return 0; 250 } 251 252 int board_late_init(void) 253 { 254 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 255 if (is_cpu_type(MXC_CPU_MX6Q)) 256 env_set("board_rev", "MX6Q"); 257 else 258 env_set("board_rev", "MX6DL"); 259 #endif 260 return 0; 261 } 262 263 int checkboard(void) 264 { 265 if (is_cpu_type(MXC_CPU_MX6Q)) 266 puts("Board: Udoo Quad\n"); 267 else 268 puts("Board: Udoo DualLite\n"); 269 270 return 0; 271 } 272
