1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2008 Extreme Engineering Solutions, Inc. 4 */ 5 6 #include <common.h> 7 #include <asm/io.h> 8 9 /* 10 * Return SYSCLK input frequency - 50 MHz or 66 MHz depending on POR config 11 */ 12 unsigned long get_board_sys_clk(ulong dummy) 13 { 14 #if defined(CONFIG_MPC85xx) 15 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 16 #elif defined(CONFIG_MPC86xx) 17 immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; 18 volatile ccsr_gur_t *gur = &immap->im_gur; 19 #endif 20 21 if (in_be32(&gur->gpporcr) & 0x10000) 22 return 66666666; 23 else 24 #ifdef CONFIG_ARCH_P2020 25 return 100000000; 26 #else 27 return 50000000; 28 #endif 29 } 30 31 #ifdef CONFIG_MPC85xx 32 /* 33 * Return DDR input clock - synchronous with SYSCLK or 66 MHz 34 * Note: 86xx doesn't support asynchronous DDR clk 35 */ 36 unsigned long get_board_ddr_clk(ulong dummy) 37 { 38 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 39 u32 ddr_ratio = (in_be32(&gur->porpllsr) & 0x00003e00) >> 9; 40 41 if (ddr_ratio == 0x7) 42 return get_board_sys_clk(dummy); 43 44 #ifdef CONFIG_ARCH_P2020 45 if (in_be32(&gur->gpporcr) & 0x20000) 46 return 66666666; 47 else 48 return 100000000; 49 #else 50 return 66666666; 51 #endif 52 } 53 #endif 54
