1 DSP side awareness for Freescale heterogeneous multicore chips based on 2 StarCore and Power Architecture 3 =============================================================== 4 powerpc/mpc85xx code ve APIs and function to get the number, 5 configuration and frequencies of all PowerPC cores and devices 6 connected to them, but it didnt have the similar code ofr HEterogeneous 7 SC3900/DSP cores and such devices like CPRI, MAPLE, MAPLE-ULB etc. 8 9 Code for DSP side awareness provides such functionality for Freescale 10 Heterogeneous SoCs which are chasis-2 compliant like B4860 and B4420 11 12 As part of this feature, following changes have been made: 13 ========================================================== 14 15 1. Changed files: 16 ================= 17 - arch/powerpc/cpu/mpc85xx/cpu.c 18 19 Code added in this file to print the DSP cores and other device's(CPRI, 20 MAPLE etc) frequencies 21 22 - arch/powerpc/cpu/mpc85xx/speed.c 23 24 Added Defines and code to extract the frequncy information for all 25 required cores and devices from RCW and System frequency 26 27 - arch/powerpc/cpu/mpc8xxx/cpu.c 28 29 Added API to get the number of SC cores in running system and Their BIT 30 MASK, similar to the code written for PowerPC 31 32 - arch/powerpc/include/asm/config_mpc85xx.h 33 34 Added top level CONFIG to identify presence of HETEROGENUOUS clusters 35 in the system and CONFIGS for SC3900/DSP components 36 37 - arch/powerpc/include/asm/processor.h 38 - include/common.h 39 40 Added newly added Functions Declaration 41 42 - include/e500.h 43 44 Global structure updated for dsp cores and other components 45 46 2. CONFIGs ADDED 47 ================ 48 49 CONFIG_HETROGENOUS_CLUSTERS - Define for checking the presence of 50 DSP/SC3900 core clusters 51 52 CONFIG_SYS_FSL_NUM_CC_PLLS - Define for number of PLLs 53 54 Though there are only 4 PLLs in B4, but in sequence of PLLs from PLL1 - 55 PLL5, PLL3 is Reserved(as mentioned in RM), so this define contains the 56 value as 5 not 4, to iterate over all PLLs while coding 57 58 CONFIG_SYS_MAPLE - Define for MAPLE Baseband Accelerator 59 CONFIG_SYS_CPRI - Define for CPRI Interface 60 CONFIG_PPC_CLUSTER_START - Start index of ppc clusters 61 CONFIG_DSP_CLUSTER_START - Start index of dsp clusters 62 63 Following are the defines for PLL's index that provide the Clocking to 64 CPRI, ULB and ETVE components 65 66 CONFIG_SYS_CPRI_CLK - Define PLL index for CPRI clock 67 CONFIG_SYS_ULB_CLK - Define PLL index for ULB clock 68 CONFIG_SYS_ETVPE_CLK - Define PLL index for ETVPE clock 69 70 3. Changes in MPC85xx_SYS_INFO Global structure 71 =============================================== 72 73 DSP cores and other device's components have been added in this structure. 74 75 freq_processor_dsp[CONFIG_MAX_DSP_CPUS] - Array to contain the DSP core's frequencies 76 freq_cpri - To store CPRI frequency 77 freq_maple - To store MAPLE frequency 78 freq_maple_ulb - To store MAPLE-ULB frequency 79 freq_maple_etvpe - To store MAPLE-eTVPE frequency 80 81 4. U-BOOT LOGS 82 ============== 83 4.1 B4860QDS board 84 Boot from NOR flash 85 86 U-Boot 2014.07-00222-g70587a8-dirty (Aug 07 2014 - 13:15:47) 87 88 CPU0: B4860E, Version: 2.0, (0x86880020) 89 Core: e6500, Version: 2.0, (0x80400020) Clock Configuration: 90 CPU0:1600 MHz, CPU1:1600 MHz, CPU2:1600 MHz, CPU3:1600 MHz, 91 DSP CPU0:1200 MHz, DSP CPU1:1200 MHz, DSP CPU2:1200 MHz, DSP CPU3:1200 MHz, 92 DSP CPU4:1200 MHz, DSP CPU5:1200 MHz, 93 CCB:666.667 MHz, 94 DDR:933.333 MHz (1866.667 MT/s data rate) (Asynchronous), IFC:166.667 MHz 95 CPRI:600 MHz 96 MAPLE:600 MHz, MAPLE-ULB:800 MHz, MAPLE-eTVPE:1000 MHz 97 FMAN1: 666.667 MHz 98 QMAN: 333.333 MHz 99 100 CPUn - PowerPC core 101 DSP CPUn - SC3900 core 102 103 Shaveta Leekha(shaveta (a] freescale.com) 104 Created August 7, 2014 105 =========================================== 106
