1 2 Notes for the MIPS architecture port of U-Boot 3 4 Toolchains 5 ---------- 6 7 http://www.denx.de/wiki/DULG/ELDK 8 ELDK < DULG < DENX 9 10 http://www.emdebian.org/crosstools.html 11 Embedded Debian -- Cross-development toolchains 12 13 http://buildroot.uclibc.org/ 14 Buildroot 15 16 Known Issues 17 ------------ 18 19 * Cache incoherency issue caused by do_bootelf_exec() at cmd_elf.c 20 21 Cache will be disabled before entering the loaded ELF image without 22 writing back and invalidating cache lines. This leads to cache 23 incoherency in most cases, unless the code gets loaded after U-Boot 24 re-initializes the cache. The more common uImage 'bootm' command does 25 not suffer this problem. 26 27 [workaround] To avoid this cache incoherency, 28 1) insert flush_cache(all) before calling dcache_disable(), or 29 2) fix dcache_disable() to do both flushing and disabling cache. 30 31 * Note that Linux users need to kill dcache_disable() in do_bootelf_exec() 32 or override do_bootelf_exec() not to disable I-/D-caches, because most 33 Linux/MIPS ports don't re-enable caches after entering kernel_entry. 34 35 TODOs 36 ----- 37 38 * Probe CPU types, I-/D-cache and TLB size etc. automatically 39 40 * Secondary cache support missing 41 42 * Initialize TLB entries redardless of their use 43 44 * R2000/R3000 class parts are not supported 45 46 * Limited testing across different MIPS variants 47 48 * Due to cache initialization issues, the DRAM on board must be 49 initialized in board specific assembler language before the cache init 50 code is run -- that is, initialize the DRAM in lowlevel_init(). 51 52 * centralize/share more CPU code of MIPS32, MIPS64 and XBurst 53 54 * support Qemu Malta 55
