1 External Debug Support 2 ---------------------- 3 4 Freescale's e500v1 and e500v2 cores (used in mpc85xx chips) have some 5 restrictions on external debugging (JTAG). In particular, for the debugger to 6 be able to receive control after a single step or breakpoint: 7 - MSR[DE] must be set 8 - A valid opcode must be fetchable, through the MMU, from the debug 9 exception vector (IVPR + IVOR15). 10 11 To maximize the time during which this requirement is met, U-Boot sets MSR[DE] 12 immediately on entry and keeps it set. It also uses a temporary TLB to keep a 13 mapping to a valid opcode at the debug exception vector, even if we normally 14 don't support exception vectors being used that early, and that's not the area 15 where U-Boot currently executes from. 16 17 Note that there may still be some small windows where debugging will not work, 18 such as in between updating IVPR and IVOR15. 19 20 Config Switches: 21 ---------------- 22 23 Please refer README section "MPC85xx External Debug Support" 24 25 Major Config Switches during various boot Modes 26 ---------------------------------------------- 27 28 NOR boot 29 !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SPL) 30 NOR boot Secure 31 !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT) 32 RAMBOOT(SD, SPI & NAND boot) 33 defined(CONFIG_SYS_RAMBOOT) 34 RAMBOOT Secure (SD, SPI & NAND) 35 defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT) 36 NAND SPL BOOT 37 defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_NAND_SPL) 38 39 40 TLB Entries during u-boot execution 41 ----------------------------------- 42 43 Note: Sequence number is in order of execution 44 45 A) defined(CONFIG_SYS_RAMBOOT) i.e. SD, SPI, NAND RAMBOOT & NAND_SPL boot 46 47 1) TLB entry to overcome e500 v1/v2 debug restriction 48 Location : Label "_start_e500" 49 TLB Entry : CONFIG_SYS_PPC_E500_DEBUG_TLB 50 EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_MONITOR_BASE 51 Properties : 256K, AS0, I, IPROT 52 53 2) TLB entry for working in AS1 54 Location : Label "create_init_ram_area" 55 TLB Entry : 15 56 EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_MONITOR_BASE 57 Properties : 1M, AS1, I, G, IPROT 58 59 3) TLB entry for the stack during AS1 60 Location : Lable "create_init_ram_area" 61 TLB Entry : 14 62 EPN -->RPN : CONFIG_SYS_INIT_RAM_ADDR --> CONFIG_SYS_INIT_RAM_ADDR 63 Properties : 16K, AS1, IPROT 64 65 4) TLB entry for CCSRBAR during AS1 execution 66 Location : cpu_init_early_f 67 TLB Entry : 13 68 EPN -->RPN : CONFIG_SYS_CCSRBAR --> CONFIG_SYS_CCSRBAR 69 Properties : 1M, AS1, I, G 70 71 5) Invalidate unproctected TLB Entries 72 Location : cpu_init_early_f 73 Invalidated: 13 74 75 6) Create TLB entries as per boards/freescale/<board>/tlb.c 76 Location : cpu_init_early_f --> init_tlbs() 77 Properties : ..., AS0, ... 78 Please note It can overwrites previous TLB Entries. 79 80 7) Disable TLB Entries of AS1 81 Location : cpu_init_f --> disable_tlb() 82 Disable : 15, 14 83 84 8) Update Flash's TLB entry 85 Location : Board_init_r 86 TLB entry : Search from TLB entries 87 EPN -->RPN : CONFIG_SYS_FLASH_BASE --> CONFIG_SYS_FLASH_BASE_PHYS 88 Properties : Board specific size, AS0, I, G, IPROT 89 90 91 B) !defined(CONFIG_SYS_RAMBOOT) i.e. NOR boot 92 93 1) TLB entry to overcome e500 v1/v2 debug restriction 94 Location : Label "_start_e500" 95 TLB Entry : CONFIG_SYS_PPC_E500_DEBUG_TLB 96 #if defined(CONFIG_SECURE_BOOT) 97 EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_PBI_FLASH_WINDOW 98 Properties : 1M, AS1, I, G, IPROT 99 #else 100 EPN -->RPN : CONFIG_SYS_MONITOR_BASE & 0xffc00000 --> 0xffc00000 101 Properties : 4M, AS0, I, G, IPROT 102 #endif 103 104 2) TLB entry for working in AS1 105 Location : Label "create_init_ram_area" 106 TLB Entry : 15 107 #if defined(CONFIG_SECURE_BOOT) 108 EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_PBI_FLASH_WINDOW 109 Properties : 1M, AS1, I, G, IPROT 110 #else 111 EPN -->RPN : CONFIG_SYS_MONITOR_BASE & 0xffc00000 --> 0xffc00000 112 Properties : 4M, AS1, I, G, IPROT 113 #endif 114 115 3) TLB entry for the stack during AS1 116 Location : Lable "create_init_ram_area" 117 TLB Entry : 14 118 EPN -->RPN : CONFIG_SYS_INIT_RAM_ADDR --> CONFIG_SYS_INIT_RAM_ADDR 119 Properties : 16K, AS1, IPROT 120 121 4) TLB entry for CCSRBAR during AS1 execution 122 Location : cpu_init_early_f 123 TLB Entry : 13 124 EPN -->RPN : CONFIG_SYS_CCSRBAR --> CONFIG_SYS_CCSRBAR 125 Properties : 1M, AS1, I, G 126 127 5) TLB entry for Errata workaround CONFIG_SYS_FSL_ERRATUM_IFC_A003399 128 Location : cpu_init_early_f 129 TLB Entry : 9 130 EPN -->RPN : SRAM_BASE_ADDR --> SRAM_BASE_ADDR 131 Properties : 1M, AS1, I 132 133 6) CONFIG_SYS_FSL_ERRATUM_IFC_A003399 Adjust flash's phys addr 134 Location : cpu_init_early_f --> setup_ifc 135 TLB Entry : Get Flash TLB 136 EPN -->RPN : Adjusted flash_phys --> Adjusted flash_phys 137 Properties : 4M, AS1, I, G, IPROT 138 139 7) CONFIG_SYS_FSL_ERRATUM_IFC_A003399: E500 v1,v2 debug restriction 140 Location : cpu_init_early_f --> setup_ifc 141 TLB Entry : CONFIG_SYS_PPC_E500_DEBUG_TLB 142 EPN -->RPN : Adjusted flash_phys --> Adjusted flash_phys 143 Properties : 4M, AS0, I, G, IPROT 144 145 8) Invalidate unproctected TLB Entries 146 Location : cpu_init_early_f 147 Invalidated: 13, 9 148 149 9) Create TLB entries as per boards/freescale/<board>/tlb.c 150 Location : cpu_init_early_f --> init_tlbs() 151 Properties : ..., AS0, ... 152 Note: It can overwrites previous TLB Entries 153 154 10) Disable TLB Entries of AS1 155 Location : cpu_init_f --> disable_tlb() 156 Disable : 15, 14 157 158 11) Create DDR's TLB entriy 159 Location : Board_init_f -> dram_init 160 TLB entry : Search free TLB entry 161 162 12) Update Flash's TLB entry 163 Location : Board_init_r 164 TLB entry : Search from TLB entries 165 EPN -->RPN : CONFIG_SYS_FLASH_BASE --> CONFIG_SYS_FLASH_BASE_PHYS 166 Properties : Board specific size, AS0, I, G, IPROT 167
