1 ---------------------------------------- 2 SOCFPGA Documentation for U-Boot and SPL 3 ---------------------------------------- 4 5 This README is about U-Boot and SPL support for Altera's ARM Cortex-A9MPCore 6 based SOCFPGA. To know more about the hardware itself, please refer to 7 www.altera.com. 8 9 10 socfpga_dw_mmc 11 -------------- 12 13 Here are macro and detailed configuration required to enable DesignWare SDMMC 14 controller support within SOCFPGA 15 16 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 17 -> Using smaller max blk cnt to avoid flooding the limited stack in OCRAM 18 19 -------------------------------------------------- 20 Generating the handoff header files for U-Boot SPL 21 -------------------------------------------------- 22 23 This text is assuming quartus 16.1, but newer versions will probably work just fine too; 24 verified with DE1_SOC_Linux_FB demo project (https://github.com/VCTLabs/DE1_SOC_Linux_FB). 25 Updated/working projects should build using either process below. 26 27 Note: it *should* work from Quartus 14.0.200 onwards, however, the current vendor demo 28 projects must have the IP cores updated as shown below. 29 30 Rebuilding your Quartus project 31 ------------------------------- 32 33 Choose one of the follwing methods, either command line or GUI. 34 35 Using the comaand line 36 ~~~~~~~~~~~~~~~~~~~~~~ 37 38 First run the embedded command shell, using your path to the Quartus install: 39 40 $ /path/to/intelFPGA/16.1/embedded/embedded_command_shell.sh 41 42 Then (if necessary) update the IP cores in the project, generate HDL code, and 43 build the project: 44 45 $ cd path/to/project/dir 46 $ qsys-generate soc_system.qsys --upgrade-ip-cores 47 $ qsys-generate soc_system.qsys --synthesis=[VERILOG|VHDL] 48 $ quartus_sh --flow compile <project name> 49 50 Convert the resulting .sof file (SRAM object file) to .rbf file (Raw bit file): 51 52 $ quartus_cpf -c <project_name>.sof soc_system.rbf 53 54 55 Generate BSP handoff files 56 ~~~~~~~~~~~~~~~~~~~~~~~~~~ 57 58 You can run the bsp editor GUI below, or run the following command from the 59 project directory: 60 61 $ /path/to/bsb/tools/bsp-create-settings --type spl --bsp-dir build \ 62 --preloader-settings-dir hps_isw_handoff/soc_system_hps_0/ \ 63 --settings build/settings.bsp 64 65 You should use the bsp "build" directory above (ie, where the settings.bsp file is) 66 in the following u-boot command to update the board headers. Once these headers 67 are updated for a given project build, u-boot should be configured for the 68 project board (eg, de0-nano-sockit) and then build the normal spl build. 69 70 Now you can skip the GUI section. 71 72 73 Using the Qsys GUI 74 ~~~~~~~~~~~~~~~~~~ 75 76 1. Navigate to your project directory 77 2. Run Quartus II 78 3. Open Project (Ctrl+J), select <project_name>.qpf 79 4. Run QSys [Tools->QSys] 80 4.1 In the Open dialog, select '<project_name>.qsys' 81 4.2 In the Open System dialog, wait until completion and press 'Close' 82 4.3 In the Qsys window, click on 'Generate HDL...' in bottom right corner 83 4.3.1 In the 'Generation' window, click 'Generate' 84 4.3.2 In the 'Generate' dialog, wait until completion and click 'Close' 85 4.4 In the QSys window, click 'Finish' 86 4.4.1 In the 'Quartus II' pop up window, click 'OK' 87 5. Back in Quartus II main window, do the following 88 5.1 Use Processing -> Start -> Start Analysis & Synthesis (Ctrl+K) 89 5.2 Use Processing -> Start Compilation (Ctrl+L) 90 91 ... this may take some time, have patience ... 92 93 6. Start the embedded command shell as shown in the previous section 94 6.1 Change directory to 'software/spl_bsp' 95 6.2 Prepare BSP by launching the BSP editor from ECS 96 => bsp-editor 97 6.3 In BSP editor 98 6.3.1 Use File -> Open 99 6.3.2 Select 'settings.bsp' file 100 6.3.3 Click Generate 101 6.3.4 Click Exit 102 103 104 Post handoff generation 105 ~~~~~~~~~~~~~~~~~~~~~~~ 106 107 Now that the handoff files are generated, U-Boot can be used to process 108 the handoff files generated by the bsp-editor. For this, please use the 109 following script from the u-boot source tree: 110 111 $ ./arch/arm/mach-socfpga/qts-filter.sh \ 112 <soc_type> \ 113 <input_qts_dir> \ 114 <input_bsp_dir> \ 115 <output_dir> 116 117 Process QTS-generated files into U-Boot compatible ones. 118 119 soc_type - Type of SoC, either 'cyclone5' or 'arria5'. 120 input_qts_dir - Directory with compiled Quartus project 121 and containing the Quartus project file (QPF). 122 input_bsp_dir - Directory with generated bsp containing 123 the settings.bsp file. 124 output_dir - Directory to store the U-Boot compatible 125 headers. 126 127 This will generate (or update) the following 4 files: 128 129 iocsr_config.h 130 pinmux_config.h 131 pll_config.h 132 sdram_config.h 133 134 These files should be copied into "qts" directory in the board directory 135 (see output argument of qts-filter.sh command above). 136 137 Here is an example for the DE-0 Nano SoC after the above rebuild process: 138 139 $ ll board/terasic/de0-nano-soc/qts/ 140 total 36 141 -rw-r--r-- 1 sarnold sarnold 8826 Mar 21 18:11 iocsr_config.h 142 -rw-r--r-- 1 sarnold sarnold 4398 Mar 21 18:11 pinmux_config.h 143 -rw-r--r-- 1 sarnold sarnold 3190 Mar 21 18:11 pll_config.h 144 -rw-r--r-- 1 sarnold sarnold 9022 Mar 21 18:11 sdram_config.h 145 146 Note: file sizes will differ slightly depending on the selected board. 147 148 Now your board is ready for full mainline support including U-Boot SPL. 149 The Preloader will not be needed any more. 150
