1 NVIDIA Tegra20 Clock And Reset Controller 2 3 This binding uses the common clock binding: 4 Documentation/devicetree/bindings/clock/clock-bindings.txt 5 6 The CAR (Clock And Reset) Controller on Tegra is the HW module responsible 7 for muxing and gating Tegra's clocks, and setting their rates. 8 9 Required properties : 10 - compatible : Should be "nvidia,tegra20-car" 11 - reg : Should contain CAR registers location and length 12 - clocks : Should contain phandle and clock specifiers for two clocks: 13 the 32 KHz "32k_in", and the board-specific oscillator "osc". 14 - #clock-cells : Should be 1. 15 In clock consumers, this cell represents the clock ID exposed by the CAR. 16 17 The first 96 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB 18 registers. These IDs often match those in the CAR's RST_DEVICES registers, 19 but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In 20 this case, those clocks are assigned IDs above 95 in order to highlight 21 this issue. Implementations that interpret these clock IDs as bit values 22 within the CLK_OUT_ENB or RST_DEVICES registers should be careful to 23 explicitly handle these special cases. 24 25 The balance of the clocks controlled by the CAR are assigned IDs of 96 and 26 above. 27 28 0 cpu 29 1 unassigned 30 2 unassigned 31 3 ac97 32 4 rtc 33 5 tmr 34 6 uart1 35 7 unassigned (register bit affects uart2 and vfir) 36 8 gpio 37 9 sdmmc2 38 10 unassigned (register bit affects spdif_in and spdif_out) 39 11 i2s1 40 12 i2c1 41 13 ndflash 42 14 sdmmc1 43 15 sdmmc4 44 16 twc 45 17 pwm 46 18 i2s2 47 19 epp 48 20 unassigned (register bit affects vi and vi_sensor) 49 21 2d 50 22 usbd 51 23 isp 52 24 3d 53 25 ide 54 26 disp2 55 27 disp1 56 28 host1x 57 29 vcp 58 30 unassigned 59 31 cache2 60 61 32 mem 62 33 ahbdma 63 34 apbdma 64 35 unassigned 65 36 kbc 66 37 stat_mon 67 38 pmc 68 39 fuse 69 40 kfuse 70 41 sbc1 71 42 snor 72 43 spi1 73 44 sbc2 74 45 xio 75 46 sbc3 76 47 dvc 77 48 dsi 78 49 unassigned (register bit affects tvo and cve) 79 50 mipi 80 51 hdmi 81 52 csi 82 53 tvdac 83 54 i2c2 84 55 uart3 85 56 unassigned 86 57 emc 87 58 usb2 88 59 usb3 89 60 mpe 90 61 vde 91 62 bsea 92 63 bsev 93 94 64 speedo 95 65 uart4 96 66 uart5 97 67 i2c3 98 68 sbc4 99 69 sdmmc3 100 70 pcie 101 71 owr 102 72 afi 103 73 csite 104 74 unassigned 105 75 avpucq 106 76 la 107 77 unassigned 108 78 unassigned 109 79 unassigned 110 80 unassigned 111 81 unassigned 112 82 unassigned 113 83 unassigned 114 84 irama 115 85 iramb 116 86 iramc 117 87 iramd 118 88 cram2 119 89 audio_2x a/k/a audio_2x_sync_clk 120 90 clk_d 121 91 unassigned 122 92 sus 123 93 cdev1 124 94 cdev2 125 95 unassigned 126 127 96 uart2 128 97 vfir 129 98 spdif_in 130 99 spdif_out 131 100 vi 132 101 vi_sensor 133 102 tvo 134 103 cve 135 104 osc 136 105 clk_32k a/k/a clk_s 137 106 clk_m 138 107 sclk 139 108 cclk 140 109 hclk 141 110 pclk 142 111 blink 143 112 pll_a 144 113 pll_a_out0 145 114 pll_c 146 115 pll_c_out1 147 116 pll_d 148 117 pll_d_out0 149 118 pll_e 150 119 pll_m 151 120 pll_m_out1 152 121 pll_p 153 122 pll_p_out1 154 123 pll_p_out2 155 124 pll_p_out3 156 125 pll_p_out4 157 126 pll_s 158 127 pll_u 159 128 pll_x 160 129 cop a/k/a avp 161 130 audio a/k/a audio_sync_clk 162 163 Example SoC include file: 164 165 / { 166 tegra_car: clock@60006000 { 167 compatible = "nvidia,tegra20-car"; 168 reg = <0x60006000 0x1000>; 169 #clock-cells = <1>; 170 }; 171 172 usb@c5004000 { 173 clocks = <&tegra_car 58>; /* usb2 */ 174 }; 175 }; 176 177 Example board file: 178 179 / { 180 clocks { 181 #address-cells = <1>; 182 #size-cells = <0>; 183 184 osc: clock { 185 compatible = "fixed-clock"; 186 #clock-cells = <0>; 187 clock-frequency = <12000000>; 188 }; 189 }; 190 191 i2c@7000d000 { 192 pmic@34 { 193 compatible = "ti,tps6586x"; 194 reg = <0x34>; 195 196 clk_32k: clock { 197 compatible = "fixed-clock"; 198 #clock-cells = <0>; 199 clock-frequency = <32768>; 200 }; 201 }; 202 }; 203 204 &tegra_car { 205 clocks = <&clk_32k> <&osc>; 206 }; 207 }; 208
