1 * Marvell Armada 37xx SoC pin and GPIO controller 2 3 Each Armada 37xx SoC comes with two pin and GPIO controllers, one for the 4 South Bridge and the other for the North Bridge. 5 6 GPIO and pin controller: 7 ------------------------ 8 9 Main node: 10 11 Refer to pinctrl-bindings.txt in this directory for details of the 12 common pinctrl bindings used by client devices, including the meaning 13 of the phrase "pin configuration node". 14 15 Required properties for pinctrl driver: 16 17 - compatible: "marvell,armada3710-sb-pinctrl", "syscon, "simple-mfd" 18 for the South Bridge 19 "marvell,armada3710-nb-pinctrl", "syscon, "simple-mfd" 20 for the North Bridge 21 - reg: The first set of registers is for pinctrl/GPIO and the second 22 set is for the interrupt controller 23 - interrupts: list of interrupts used by the GPIO 24 25 Available groups and functions for the North Bridge: 26 27 group: jtag 28 - pins 20-24 29 - functions jtag, gpio 30 31 group sdio0 32 - pins 8-10 33 - functions sdio, gpio 34 35 group emmc_nb 36 - pins 27-35 37 - functions emmc, gpio 38 39 group pwm0 40 - pin 11 (GPIO1-11) 41 - functions pwm, gpio 42 43 group pwm1 44 - pin 12 45 - functions pwm, gpio 46 47 group pwm2 48 - pin 13 49 - functions pwm, gpio 50 51 group pwm3 52 - pin 14 53 - functions pwm, gpio 54 55 group pmic1 56 - pin 7 57 - functions pmic, gpio 58 59 group pmic0 60 - pin 6 61 - functions pmic, gpio 62 63 group i2c2 64 - pins 2-3 65 - functions i2c, gpio 66 67 group i2c1 68 - pins 0-1 69 - functions i2c, gpio 70 71 group spi_cs1 72 - pin 17 73 - functions spi, gpio 74 75 group spi_cs2 76 - pin 18 77 - functions spi, gpio 78 79 group spi_cs3 80 - pin 19 81 - functions spi, gpio 82 83 group onewire 84 - pin 4 85 - functions onewire, gpio 86 87 group uart1 88 - pins 25-26 89 - functions uart, gpio 90 91 group spi_quad 92 - pins 15-16 93 - functions spi, gpio 94 95 group uart_2 96 - pins 9-10 97 - functions uart, gpio 98 99 Available groups and functions for the South Bridge: 100 101 group usb32_drvvbus0 102 - pin 36 103 - functions drvbus, gpio 104 105 group usb2_drvvbus1 106 - pin 37 107 - functions drvbus, gpio 108 109 group sdio_sb 110 - pins 60-65 111 - functions sdio, gpio 112 113 group rgmii 114 - pins 42-53 115 - functions mii, gpio 116 117 group pcie1 118 - pins 39-41 119 - functions pcie, gpio 120 121 group smi 122 - pins 54-55 123 - functions smi, gpio 124 125 group ptp 126 - pins 56-58 127 - functions ptp, gpio 128 129 group ptp_clk 130 - pin 57 131 - functions ptp, mii 132 133 group ptp_trig 134 - pin 58 135 - functions ptp, mii 136 137 group mii_col 138 - pin 59 139 - functions mii, mii_err 140 141 GPIO subnode: 142 143 Please refer to gpio.txt in "gpio" directory for details of gpio-ranges property 144 and the common GPIO bindings used by client devices. 145 146 Required properties for the GPIO driver under the gpio subnode: 147 - interrupts: List of interrupt specifiers for the controllers interrupt. 148 - gpio-controller: Marks the device node as a GPIO controller. 149 - #gpio-cells: Should be 2. The first cell is the GPIO number and the 150 second cell specifies GPIO flags, as defined in 151 <dt-bindings/gpio/gpio.h>. Only the GPIO_ACTIVE_HIGH and 152 GPIO_ACTIVE_LOW flags are supported. 153 - gpio-ranges: Range of pins managed by the GPIO controller. 154 155 Example: 156 pinctrl_sb: pinctrl-sb@18800 { 157 compatible = "marvell,armada3710-sb-pinctrl", 158 "syscon", "simple-mfd"; 159 reg = <0x18800 0x100>, <0x18C00 0x20>; 160 gpiosb: gpiosb { 161 #gpio-cells = <2>; 162 gpio-ranges = <&pinctrl_sb 0 0 30>; 163 gpio-controller; 164 interrupts = 165 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 166 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 167 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 168 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 169 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 170 }; 171 172 rgmii_pins: mii-pins { 173 groups = "rgmii"; 174 function = "mii"; 175 }; 176 177 sdio_pins: sdio-pins { 178 groups = "sdio_sb"; 179 function = "sdio"; 180 }; 181 182 pcie_pins: pcie-pins { 183 groups = "pcie1"; 184 function = "pcie"; 185 }; 186 };
