1 * Rockchip Pinmux Controller 2 3 The Rockchip Pinmux Controller, enables the IC 4 to share one PAD to several functional blocks. The sharing is done by 5 multiplexing the PAD input/output signals. For each PAD there are several 6 muxing options with option 0 being the use as a GPIO. 7 8 Please refer to pinctrl-bindings.txt in this directory for details of the 9 common pinctrl bindings used by client devices, including the meaning of the 10 phrase "pin configuration node". 11 12 The Rockchip pin configuration node is a node of a group of pins which can be 13 used for a specific device or function. This node represents both mux and 14 config of the pins in that group. The 'pins' selects the function mode(also 15 named pin mode) this pin can work on and the 'config' configures various pad 16 settings such as pull-up, etc. 17 18 The pins are grouped into up to 5 individual pin banks which need to be 19 defined as gpio sub-nodes of the pinmux controller. 20 21 Required properties for iomux controller: 22 - compatible: one of "rockchip,rk2928-pinctrl", "rockchip,rk3066a-pinctrl" 23 "rockchip,rk3066b-pinctrl", "rockchip,rk3188-pinctrl" 24 "rockchip,rk3288-pinctrl" 25 - rockchip,grf: phandle referencing a syscon providing the 26 "general register files" 27 28 Optional properties for iomux controller: 29 - rockchip,pmu: phandle referencing a syscon providing the pmu registers 30 as some SoCs carry parts of the iomux controller registers there. 31 Required for at least rk3188 and rk3288. 32 33 Deprecated properties for iomux controller: 34 - reg: first element is the general register space of the iomux controller 35 It should be large enough to contain also separate pull registers. 36 second element is the separate pull register space of the rk3188. 37 Use rockchip,grf and rockchip,pmu described above instead. 38 39 Required properties for gpio sub nodes: 40 - compatible: "rockchip,gpio-bank" 41 - reg: register of the gpio bank (different than the iomux registerset) 42 - interrupts: base interrupt of the gpio bank in the interrupt controller 43 - clocks: clock that drives this bank 44 - gpio-controller: identifies the node as a gpio controller and pin bank. 45 - #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO 46 binding is used, the amount of cells must be specified as 2. See generic 47 GPIO binding documentation for description of particular cells. 48 - interrupt-controller: identifies the controller node as interrupt-parent. 49 - #interrupt-cells: the value of this property should be 2 and the interrupt 50 cells should use the standard two-cell scheme described in 51 bindings/interrupt-controller/interrupts.txt 52 53 Deprecated properties for gpio sub nodes: 54 - compatible: "rockchip,rk3188-gpio-bank0" 55 - reg: second element: separate pull register for rk3188 bank0, use 56 rockchip,pmu described above instead 57 58 Required properties for pin configuration node: 59 - rockchip,pins: 3 integers array, represents a group of pins mux and config 60 setting. The format is rockchip,pins = <PIN_BANK PIN_BANK_IDX MUX &phandle>. 61 The MUX 0 means gpio and MUX 1 to N mean the specific device function. 62 The phandle of a node containing the generic pinconfig options 63 to use, as described in pinctrl-bindings.txt in this directory. 64 65 Examples: 66 67 #include <dt-bindings/pinctrl/rockchip.h> 68 69 ... 70 71 pinctrl@20008000 { 72 compatible = "rockchip,rk3066a-pinctrl"; 73 rockchip,grf = <&grf>; 74 75 #address-cells = <1>; 76 #size-cells = <1>; 77 ranges; 78 79 gpio0: gpio0@20034000 { 80 compatible = "rockchip,gpio-bank"; 81 reg = <0x20034000 0x100>; 82 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 83 clocks = <&clk_gates8 9>; 84 85 gpio-controller; 86 #gpio-cells = <2>; 87 88 interrupt-controller; 89 #interrupt-cells = <2>; 90 }; 91 92 ... 93 94 pcfg_pull_default: pcfg_pull_default { 95 bias-pull-pin-default 96 }; 97 98 uart2 { 99 uart2_xfer: uart2-xfer { 100 rockchip,pins = <RK_GPIO1 8 1 &pcfg_pull_default>, 101 <RK_GPIO1 9 1 &pcfg_pull_default>; 102 }; 103 }; 104 }; 105 106 uart2: serial@20064000 { 107 compatible = "snps,dw-apb-uart"; 108 reg = <0x20064000 0x400>; 109 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 110 reg-shift = <2>; 111 reg-io-width = <1>; 112 clocks = <&mux_uart2>; 113 status = "okay"; 114 115 pinctrl-names = "default"; 116 pinctrl-0 = <&uart2_xfer>; 117 }; 118 119 Example for rk3188: 120 121 pinctrl@20008000 { 122 compatible = "rockchip,rk3188-pinctrl"; 123 rockchip,grf = <&grf>; 124 rockchip,pmu = <&pmu>; 125 #address-cells = <1>; 126 #size-cells = <1>; 127 ranges; 128 129 gpio0: gpio0@0x2000a000 { 130 compatible = "rockchip,rk3188-gpio-bank0"; 131 reg = <0x2000a000 0x100>; 132 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 133 clocks = <&clk_gates8 9>; 134 135 gpio-controller; 136 #gpio-cells = <2>; 137 138 interrupt-controller; 139 #interrupt-cells = <2>; 140 }; 141 142 gpio1: gpio1@0x2003c000 { 143 compatible = "rockchip,gpio-bank"; 144 reg = <0x2003c000 0x100>; 145 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 146 clocks = <&clk_gates8 10>; 147 148 gpio-controller; 149 #gpio-cells = <2>; 150 151 interrupt-controller; 152 #interrupt-cells = <2>; 153 }; 154 155 ... 156 157 }; 158
