1 ST,stm32mp1 DDR3/LPDDR2/LPDDR3 Controller (DDRCTRL and DDRPHYC) 2 3 -------------------- 4 Required properties: 5 -------------------- 6 - compatible : Should be "st,stm32mp1-ddr" 7 - reg : controleur (DDRCTRL) and phy (DDRPHYC) base address 8 - clocks : controller clocks handle 9 - clock-names : associated controller clock names 10 the "ddrphyc" clock is used to check the DDR frequency 11 at phy level according the expected value in "mem-speed" field 12 13 the next attributes are DDR parameters, they are generated by DDR tools 14 included in STM32 Cube tool 15 16 info attributes: 17 ---------------- 18 - st,mem-name : name for DDR configuration, simple string for information 19 - st,mem-speed : DDR expected speed for the setting in MHz 20 - st,mem-size : DDR mem size in byte 21 22 23 controlleur attributes: 24 ----------------------- 25 - st,ctl-reg : controleur values depending of the DDR type 26 (DDR3/LPDDR2/LPDDR3) 27 for STM32MP15x: 25 values are requested in this order 28 MSTR 29 MRCTRL0 30 MRCTRL1 31 DERATEEN 32 DERATEINT 33 PWRCTL 34 PWRTMG 35 HWLPCTL 36 RFSHCTL0 37 RFSHCTL3 38 CRCPARCTL0 39 ZQCTL0 40 DFITMG0 41 DFITMG1 42 DFILPCFG0 43 DFIUPD0 44 DFIUPD1 45 DFIUPD2 46 DFIPHYMSTR 47 ODTMAP 48 DBG0 49 DBG1 50 DBGCMD 51 POISONCFG 52 PCCFG 53 54 - st,ctl-timing : controleur values depending of frequency and timing parameter 55 of DDR 56 for STM32MP15x: 12 values are requested in this order 57 RFSHTMG 58 DRAMTMG0 59 DRAMTMG1 60 DRAMTMG2 61 DRAMTMG3 62 DRAMTMG4 63 DRAMTMG5 64 DRAMTMG6 65 DRAMTMG7 66 DRAMTMG8 67 DRAMTMG14 68 ODTCFG 69 70 - st,ctl-map : controleur values depending of address mapping 71 for STM32MP15x: 9 values are requested in this order 72 ADDRMAP1 73 ADDRMAP2 74 ADDRMAP3 75 ADDRMAP4 76 ADDRMAP5 77 ADDRMAP6 78 ADDRMAP9 79 ADDRMAP10 80 ADDRMAP11 81 82 - st,ctl-perf : controleur values depending of performance and scheduling 83 for STM32MP15x: 17 values are requested in this order 84 SCHED 85 SCHED1 86 PERFHPR1 87 PERFLPR1 88 PERFWR1 89 PCFGR_0 90 PCFGW_0 91 PCFGQOS0_0 92 PCFGQOS1_0 93 PCFGWQOS0_0 94 PCFGWQOS1_0 95 PCFGR_1 96 PCFGW_1 97 PCFGQOS0_1 98 PCFGQOS1_1 99 PCFGWQOS0_1 100 PCFGWQOS1_1 101 102 phyc attributes: 103 ---------------- 104 - st,phy-reg : phy values depending of the DDR type (DDR3/LPDDR2/LPDDR3) 105 for STM32MP15x: 10 values are requested in this order 106 PGCR 107 ACIOCR 108 DXCCR 109 DSGCR 110 DCR 111 ODTCR 112 ZQ0CR1 113 DX0GCR 114 DX1GCR 115 DX2GCR 116 DX3GCR 117 118 - st,phy-timing : phy values depending of frequency and timing parameter of DDR 119 for STM32MP15x: 10 values are requested in this order 120 PTR0 121 PTR1 122 PTR2 123 DTPR0 124 DTPR1 125 DTPR2 126 MR0 127 MR1 128 MR2 129 MR3 130 131 - st,phy-cal : phy cal depending of calibration or tuning of DDR 132 for STM32MP15x: 12 values are requested in this order 133 DX0DLLCR 134 DX0DQTR 135 DX0DQSTR 136 DX1DLLCR 137 DX1DQTR 138 DX1DQSTR 139 DX2DLLCR 140 DX2DQTR 141 DX2DQSTR 142 DX3DLLCR 143 DX3DQTR 144 DX3DQSTR 145 146 Example: 147 148 / { 149 soc { 150 u-boot,dm-spl; 151 152 ddr: ddr@0x5A003000{ 153 u-boot,dm-spl; 154 u-boot,dm-pre-reloc; 155 156 compatible = "st,stm32mp1-ddr"; 157 158 reg = <0x5A003000 0x550 159 0x5A004000 0x234>; 160 161 clocks = <&rcc_clk AXIDCG>, 162 <&rcc_clk DDRC1>, 163 <&rcc_clk DDRC2>, 164 <&rcc_clk DDRPHYC>, 165 <&rcc_clk DDRCAPB>, 166 <&rcc_clk DDRPHYCAPB>; 167 168 clock-names = "axidcg", 169 "ddrc1", 170 "ddrc2", 171 "ddrphyc", 172 "ddrcapb", 173 "ddrphycapb"; 174 175 st,mem-name = "DDR3 2x4Gb 533MHz"; 176 st,mem-speed = <533>; 177 st,mem-size = <0x40000000>; 178 179 st,ctl-reg = < 180 0x00040401 /*MSTR*/ 181 0x00000010 /*MRCTRL0*/ 182 0x00000000 /*MRCTRL1*/ 183 0x00000000 /*DERATEEN*/ 184 0x00800000 /*DERATEINT*/ 185 0x00000000 /*PWRCTL*/ 186 0x00400010 /*PWRTMG*/ 187 0x00000000 /*HWLPCTL*/ 188 0x00210000 /*RFSHCTL0*/ 189 0x00000000 /*RFSHCTL3*/ 190 0x00000000 /*CRCPARCTL0*/ 191 0xC2000040 /*ZQCTL0*/ 192 0x02050105 /*DFITMG0*/ 193 0x00000202 /*DFITMG1*/ 194 0x07000000 /*DFILPCFG0*/ 195 0xC0400003 /*DFIUPD0*/ 196 0x00000000 /*DFIUPD1*/ 197 0x00000000 /*DFIUPD2*/ 198 0x00000000 /*DFIPHYMSTR*/ 199 0x00000001 /*ODTMAP*/ 200 0x00000000 /*DBG0*/ 201 0x00000000 /*DBG1*/ 202 0x00000000 /*DBGCMD*/ 203 0x00000000 /*POISONCFG*/ 204 0x00000010 /*PCCFG*/ 205 >; 206 207 st,ctl-timing = < 208 0x0080008A /*RFSHTMG*/ 209 0x121B2414 /*DRAMTMG0*/ 210 0x000D041B /*DRAMTMG1*/ 211 0x0607080E /*DRAMTMG2*/ 212 0x0050400C /*DRAMTMG3*/ 213 0x07040407 /*DRAMTMG4*/ 214 0x06060303 /*DRAMTMG5*/ 215 0x02020002 /*DRAMTMG6*/ 216 0x00000202 /*DRAMTMG7*/ 217 0x00001005 /*DRAMTMG8*/ 218 0x000D041B /*DRAMTMG1*/4 219 0x06000600 /*ODTCFG*/ 220 >; 221 222 st,ctl-map = < 223 0x00080808 /*ADDRMAP1*/ 224 0x00000000 /*ADDRMAP2*/ 225 0x00000000 /*ADDRMAP3*/ 226 0x00001F1F /*ADDRMAP4*/ 227 0x07070707 /*ADDRMAP5*/ 228 0x0F070707 /*ADDRMAP6*/ 229 0x00000000 /*ADDRMAP9*/ 230 0x00000000 /*ADDRMAP10*/ 231 0x00000000 /*ADDRMAP11*/ 232 >; 233 234 st,ctl-perf = < 235 0x00001201 /*SCHED*/ 236 0x00001201 /*SCHED*/1 237 0x01000001 /*PERFHPR1*/ 238 0x08000200 /*PERFLPR1*/ 239 0x08000400 /*PERFWR1*/ 240 0x00010000 /*PCFGR_0*/ 241 0x00000000 /*PCFGW_0*/ 242 0x02100B03 /*PCFGQOS0_0*/ 243 0x00800100 /*PCFGQOS1_0*/ 244 0x01100B03 /*PCFGWQOS0_0*/ 245 0x01000200 /*PCFGWQOS1_0*/ 246 0x00010000 /*PCFGR_1*/ 247 0x00000000 /*PCFGW_1*/ 248 0x02100B03 /*PCFGQOS0_1*/ 249 0x00800000 /*PCFGQOS1_1*/ 250 0x01100B03 /*PCFGWQOS0_1*/ 251 0x01000200 /*PCFGWQOS1_1*/ 252 >; 253 254 st,phy-reg = < 255 0x01442E02 /*PGCR*/ 256 0x10400812 /*ACIOCR*/ 257 0x00000C40 /*DXCCR*/ 258 0xF200001F /*DSGCR*/ 259 0x0000000B /*DCR*/ 260 0x00010000 /*ODTCR*/ 261 0x0000007B /*ZQ0CR1*/ 262 0x0000CE81 /*DX0GCR*/ 263 0x0000CE81 /*DX1GCR*/ 264 0x0000CE81 /*DX2GCR*/ 265 0x0000CE81 /*DX3GCR*/ 266 >; 267 268 st,phy-timing = < 269 0x0022A41B /*PTR0*/ 270 0x047C0740 /*PTR1*/ 271 0x042D9C80 /*PTR2*/ 272 0x369477D0 /*DTPR0*/ 273 0x098A00D8 /*DTPR1*/ 274 0x10023600 /*DTPR2*/ 275 0x00000830 /*MR0*/ 276 0x00000000 /*MR1*/ 277 0x00000208 /*MR2*/ 278 0x00000000 /*MR3*/ 279 >; 280 281 st,phy-cal = < 282 0x40000000 /*DX0DLLCR*/ 283 0xFFFFFFFF /*DX0DQTR*/ 284 0x3DB02000 /*DX0DQSTR*/ 285 0x40000000 /*DX1DLLCR*/ 286 0xFFFFFFFF /*DX1DQTR*/ 287 0x3DB02000 /*DX1DQSTR*/ 288 0x40000000 /*DX2DLLCR*/ 289 0xFFFFFFFF /*DX2DQTR*/ 290 0x3DB02000 /*DX2DQSTR*/ 291 0x40000000 /*DX3DLLCR*/ 292 0xFFFFFFFF /*DX3DQTR*/ 293 0x3DB02000 /*DX3DQSTR*/ 294 >; 295 296 status = "okay"; 297 }; 298 }; 299 }; 300
