1 /* 2 * r8a7790 Clock Pulse Generator / Module Standby and Software Reset 3 * 4 * Copyright (C) 2017 Glider bvba 5 * 6 * Based on clk-rcar-gen2.c 7 * 8 * Copyright (C) 2013 Ideas On Board SPRL 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; version 2 of the License. 13 */ 14 15 #include <common.h> 16 #include <clk-uclass.h> 17 #include <dm.h> 18 19 #include <dt-bindings/clock/r8a7790-cpg-mssr.h> 20 21 #include "renesas-cpg-mssr.h" 22 #include "rcar-gen2-cpg.h" 23 24 enum clk_ids { 25 /* Core Clock Outputs exported to DT */ 26 LAST_DT_CORE_CLK = R8A7790_CLK_OSC, 27 28 /* External Input Clocks */ 29 CLK_EXTAL, 30 CLK_USB_EXTAL, 31 32 /* Internal Core Clocks */ 33 CLK_MAIN, 34 CLK_PLL0, 35 CLK_PLL1, 36 CLK_PLL3, 37 CLK_PLL1_DIV2, 38 39 /* Module Clocks */ 40 MOD_CLK_BASE 41 }; 42 43 static const struct cpg_core_clk r8a7790_core_clks[] = { 44 /* External Clock Inputs */ 45 DEF_INPUT("extal", CLK_EXTAL), 46 DEF_INPUT("usb_extal", CLK_USB_EXTAL), 47 48 /* Internal Core Clocks */ 49 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL), 50 DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN), 51 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN), 52 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN), 53 54 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), 55 56 /* Core Clock Outputs */ 57 DEF_BASE("z", R8A7790_CLK_Z, CLK_TYPE_GEN2_Z, CLK_PLL0), 58 DEF_BASE("lb", R8A7790_CLK_LB, CLK_TYPE_GEN2_LB, CLK_PLL1), 59 DEF_BASE("adsp", R8A7790_CLK_ADSP, CLK_TYPE_GEN2_ADSP, CLK_PLL1), 60 DEF_BASE("sdh", R8A7790_CLK_SDH, CLK_TYPE_GEN2_SDH, CLK_PLL1), 61 DEF_BASE("sd0", R8A7790_CLK_SD0, CLK_TYPE_GEN2_SD0, CLK_PLL1), 62 DEF_BASE("sd1", R8A7790_CLK_SD1, CLK_TYPE_GEN2_SD1, CLK_PLL1), 63 DEF_BASE("qspi", R8A7790_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2), 64 DEF_BASE("rcan", R8A7790_CLK_RCAN, CLK_TYPE_GEN2_RCAN, CLK_USB_EXTAL), 65 66 DEF_FIXED("z2", R8A7790_CLK_Z2, CLK_PLL1, 2, 1), 67 DEF_FIXED("zg", R8A7790_CLK_ZG, CLK_PLL1, 3, 1), 68 DEF_FIXED("zx", R8A7790_CLK_ZX, CLK_PLL1, 3, 1), 69 DEF_FIXED("zs", R8A7790_CLK_ZS, CLK_PLL1, 6, 1), 70 DEF_FIXED("hp", R8A7790_CLK_HP, CLK_PLL1, 12, 1), 71 DEF_FIXED("i", R8A7790_CLK_I, CLK_PLL1, 2, 1), 72 DEF_FIXED("b", R8A7790_CLK_B, CLK_PLL1, 12, 1), 73 DEF_FIXED("p", R8A7790_CLK_P, CLK_PLL1, 24, 1), 74 DEF_FIXED("cl", R8A7790_CLK_CL, CLK_PLL1, 48, 1), 75 DEF_FIXED("m2", R8A7790_CLK_M2, CLK_PLL1, 8, 1), 76 DEF_FIXED("imp", R8A7790_CLK_IMP, CLK_PLL1, 4, 1), 77 DEF_FIXED("zb3", R8A7790_CLK_ZB3, CLK_PLL3, 4, 1), 78 DEF_FIXED("zb3d2", R8A7790_CLK_ZB3D2, CLK_PLL3, 8, 1), 79 DEF_FIXED("ddr", R8A7790_CLK_DDR, CLK_PLL3, 8, 1), 80 DEF_FIXED("mp", R8A7790_CLK_MP, CLK_PLL1_DIV2, 15, 1), 81 DEF_FIXED("cp", R8A7790_CLK_CP, CLK_EXTAL, 2, 1), 82 DEF_FIXED("r", R8A7790_CLK_R, CLK_PLL1, 49152, 1), 83 DEF_FIXED("osc", R8A7790_CLK_OSC, CLK_PLL1, 12288, 1), 84 85 DEF_DIV6P1("sd2", R8A7790_CLK_SD2, CLK_PLL1_DIV2, 0x078), 86 DEF_DIV6P1("sd3", R8A7790_CLK_SD3, CLK_PLL1_DIV2, 0x26c), 87 DEF_DIV6P1("mmc0", R8A7790_CLK_MMC0, CLK_PLL1_DIV2, 0x240), 88 DEF_DIV6P1("mmc1", R8A7790_CLK_MMC1, CLK_PLL1_DIV2, 0x244), 89 DEF_DIV6P1("ssp", R8A7790_CLK_SSP, CLK_PLL1_DIV2, 0x248), 90 DEF_DIV6P1("ssprs", R8A7790_CLK_SSPRS, CLK_PLL1_DIV2, 0x24c), 91 }; 92 93 static const struct mssr_mod_clk r8a7790_mod_clks[] = { 94 DEF_MOD("msiof0", 0, R8A7790_CLK_MP), 95 DEF_MOD("vcp1", 100, R8A7790_CLK_ZS), 96 DEF_MOD("vcp0", 101, R8A7790_CLK_ZS), 97 DEF_MOD("vpc1", 102, R8A7790_CLK_ZS), 98 DEF_MOD("vpc0", 103, R8A7790_CLK_ZS), 99 DEF_MOD("jpu", 106, R8A7790_CLK_M2), 100 DEF_MOD("ssp1", 109, R8A7790_CLK_ZS), 101 DEF_MOD("tmu1", 111, R8A7790_CLK_P), 102 DEF_MOD("3dg", 112, R8A7790_CLK_ZG), 103 DEF_MOD("2d-dmac", 115, R8A7790_CLK_ZS), 104 DEF_MOD("fdp1-2", 117, R8A7790_CLK_ZS), 105 DEF_MOD("fdp1-1", 118, R8A7790_CLK_ZS), 106 DEF_MOD("fdp1-0", 119, R8A7790_CLK_ZS), 107 DEF_MOD("tmu3", 121, R8A7790_CLK_P), 108 DEF_MOD("tmu2", 122, R8A7790_CLK_P), 109 DEF_MOD("cmt0", 124, R8A7790_CLK_R), 110 DEF_MOD("tmu0", 125, R8A7790_CLK_CP), 111 DEF_MOD("vsp1du1", 127, R8A7790_CLK_ZS), 112 DEF_MOD("vsp1du0", 128, R8A7790_CLK_ZS), 113 DEF_MOD("vsp1-rt", 130, R8A7790_CLK_ZS), 114 DEF_MOD("vsp1-sy", 131, R8A7790_CLK_ZS), 115 DEF_MOD("scifa2", 202, R8A7790_CLK_MP), 116 DEF_MOD("scifa1", 203, R8A7790_CLK_MP), 117 DEF_MOD("scifa0", 204, R8A7790_CLK_MP), 118 DEF_MOD("msiof2", 205, R8A7790_CLK_MP), 119 DEF_MOD("scifb0", 206, R8A7790_CLK_MP), 120 DEF_MOD("scifb1", 207, R8A7790_CLK_MP), 121 DEF_MOD("msiof1", 208, R8A7790_CLK_MP), 122 DEF_MOD("msiof3", 215, R8A7790_CLK_MP), 123 DEF_MOD("scifb2", 216, R8A7790_CLK_MP), 124 DEF_MOD("sys-dmac1", 218, R8A7790_CLK_ZS), 125 DEF_MOD("sys-dmac0", 219, R8A7790_CLK_ZS), 126 DEF_MOD("iic2", 300, R8A7790_CLK_HP), 127 DEF_MOD("tpu0", 304, R8A7790_CLK_CP), 128 DEF_MOD("mmcif1", 305, R8A7790_CLK_MMC1), 129 DEF_MOD("scif2", 310, R8A7790_CLK_P), 130 DEF_MOD("sdhi3", 311, R8A7790_CLK_SD3), 131 DEF_MOD("sdhi2", 312, R8A7790_CLK_SD2), 132 DEF_MOD("sdhi1", 313, R8A7790_CLK_SD1), 133 DEF_MOD("sdhi0", 314, R8A7790_CLK_SD0), 134 DEF_MOD("mmcif0", 315, R8A7790_CLK_MMC0), 135 DEF_MOD("iic0", 318, R8A7790_CLK_HP), 136 DEF_MOD("pciec", 319, R8A7790_CLK_MP), 137 DEF_MOD("iic1", 323, R8A7790_CLK_HP), 138 DEF_MOD("usb3.0", 328, R8A7790_CLK_MP), 139 DEF_MOD("cmt1", 329, R8A7790_CLK_R), 140 DEF_MOD("usbhs-dmac0", 330, R8A7790_CLK_HP), 141 DEF_MOD("usbhs-dmac1", 331, R8A7790_CLK_HP), 142 DEF_MOD("irqc", 407, R8A7790_CLK_CP), 143 DEF_MOD("intc-sys", 408, R8A7790_CLK_ZS), 144 DEF_MOD("audio-dmac1", 501, R8A7790_CLK_HP), 145 DEF_MOD("audio-dmac0", 502, R8A7790_CLK_HP), 146 DEF_MOD("adsp_mod", 506, R8A7790_CLK_ADSP), 147 DEF_MOD("thermal", 522, CLK_EXTAL), 148 DEF_MOD("pwm", 523, R8A7790_CLK_P), 149 DEF_MOD("usb-ehci", 703, R8A7790_CLK_MP), 150 DEF_MOD("usbhs", 704, R8A7790_CLK_HP), 151 DEF_MOD("hscif1", 716, R8A7790_CLK_ZS), 152 DEF_MOD("hscif0", 717, R8A7790_CLK_ZS), 153 DEF_MOD("scif1", 720, R8A7790_CLK_P), 154 DEF_MOD("scif0", 721, R8A7790_CLK_P), 155 DEF_MOD("du2", 722, R8A7790_CLK_ZX), 156 DEF_MOD("du1", 723, R8A7790_CLK_ZX), 157 DEF_MOD("du0", 724, R8A7790_CLK_ZX), 158 DEF_MOD("lvds1", 725, R8A7790_CLK_ZX), 159 DEF_MOD("lvds0", 726, R8A7790_CLK_ZX), 160 DEF_MOD("mlb", 802, R8A7790_CLK_HP), 161 DEF_MOD("vin3", 808, R8A7790_CLK_ZG), 162 DEF_MOD("vin2", 809, R8A7790_CLK_ZG), 163 DEF_MOD("vin1", 810, R8A7790_CLK_ZG), 164 DEF_MOD("vin0", 811, R8A7790_CLK_ZG), 165 DEF_MOD("etheravb", 812, R8A7790_CLK_HP), 166 DEF_MOD("ether", 813, R8A7790_CLK_P), 167 DEF_MOD("sata1", 814, R8A7790_CLK_ZS), 168 DEF_MOD("sata0", 815, R8A7790_CLK_ZS), 169 DEF_MOD("gyro-adc", 901, R8A7790_CLK_P), 170 DEF_MOD("gpio5", 907, R8A7790_CLK_CP), 171 DEF_MOD("gpio4", 908, R8A7790_CLK_CP), 172 DEF_MOD("gpio3", 909, R8A7790_CLK_CP), 173 DEF_MOD("gpio2", 910, R8A7790_CLK_CP), 174 DEF_MOD("gpio1", 911, R8A7790_CLK_CP), 175 DEF_MOD("gpio0", 912, R8A7790_CLK_CP), 176 DEF_MOD("can1", 915, R8A7790_CLK_P), 177 DEF_MOD("can0", 916, R8A7790_CLK_P), 178 DEF_MOD("qspi_mod", 917, R8A7790_CLK_QSPI), 179 DEF_MOD("iicdvfs", 926, R8A7790_CLK_CP), 180 DEF_MOD("i2c3", 928, R8A7790_CLK_HP), 181 DEF_MOD("i2c2", 929, R8A7790_CLK_HP), 182 DEF_MOD("i2c1", 930, R8A7790_CLK_HP), 183 DEF_MOD("i2c0", 931, R8A7790_CLK_HP), 184 DEF_MOD("ssi-all", 1005, R8A7790_CLK_P), 185 DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)), 186 DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)), 187 DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)), 188 DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)), 189 DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)), 190 DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)), 191 DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)), 192 DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)), 193 DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)), 194 DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)), 195 DEF_MOD("scu-all", 1017, R8A7790_CLK_P), 196 DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)), 197 DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)), 198 DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)), 199 DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)), 200 DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)), 201 DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)), 202 DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)), 203 DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)), 204 DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)), 205 DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)), 206 DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)), 207 DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)), 208 DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)), 209 DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)), 210 }; 211 212 /* 213 * CPG Clock Data 214 */ 215 216 /* 217 * MD EXTAL PLL0 PLL1 PLL3 218 * 14 13 19 (MHz) *1 *1 219 *--------------------------------------------------- 220 * 0 0 0 15 x172/2 x208/2 x106 221 * 0 0 1 15 x172/2 x208/2 x88 222 * 0 1 0 20 x130/2 x156/2 x80 223 * 0 1 1 20 x130/2 x156/2 x66 224 * 1 0 0 26 / 2 x200/2 x240/2 x122 225 * 1 0 1 26 / 2 x200/2 x240/2 x102 226 * 1 1 0 30 / 2 x172/2 x208/2 x106 227 * 1 1 1 30 / 2 x172/2 x208/2 x88 228 * 229 * *1 : Table 7.5a indicates VCO output (PLLx = VCO/2) 230 */ 231 #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \ 232 (((md) & BIT(13)) >> 12) | \ 233 (((md) & BIT(19)) >> 19)) 234 static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] = { 235 { 1, 208, 106 }, { 1, 208, 88 }, { 1, 156, 80 }, { 1, 156, 66 }, 236 { 2, 240, 122 }, { 2, 240, 102 }, { 2, 208, 106 }, { 2, 208, 88 }, 237 }; 238 239 static const struct mstp_stop_table r8a7790_mstp_table[] = { 240 { 0x00640801, 0x400000, 0x00640801, 0x0 }, 241 { 0xDB6E9BDF, 0x0, 0xDB6E9BDF, 0x0 }, 242 { 0x300DA1FC, 0x2010, 0x300DA1FC, 0x0 }, 243 { 0xF08CF831, 0x0, 0xF08CF831, 0x0 }, 244 { 0x80000184, 0x180, 0x80000184, 0x0 }, 245 { 0x44C00046, 0x0, 0x44C00046, 0x0 }, 246 { 0x0, 0x0, 0x0, 0x0 }, /* SMSTP6 is not present on Gen2 */ 247 { 0x07F30718, 0x200000, 0x07F30718, 0x0 }, 248 { 0x01F0FF84, 0x0, 0x01F0FF84, 0x0 }, 249 { 0xF5979FCF, 0x0, 0xF5979FCF, 0x0 }, 250 { 0xFFFEFFE0, 0x0, 0xFFFEFFE0, 0x0 }, 251 { 0x00000000, 0x0, 0x00000000, 0x0 }, 252 }; 253 254 static const void *r8a7790_get_pll_config(const u32 cpg_mode) 255 { 256 return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; 257 } 258 259 static const struct cpg_mssr_info r8a7790_cpg_mssr_info = { 260 .core_clk = r8a7790_core_clks, 261 .core_clk_size = ARRAY_SIZE(r8a7790_core_clks), 262 .mod_clk = r8a7790_mod_clks, 263 .mod_clk_size = ARRAY_SIZE(r8a7790_mod_clks), 264 .mstp_table = r8a7790_mstp_table, 265 .mstp_table_size = ARRAY_SIZE(r8a7790_mstp_table), 266 .reset_node = "renesas,r8a7790-rst", 267 .extal_usb_node = "usb_extal", 268 .mod_clk_base = MOD_CLK_BASE, 269 .clk_extal_id = CLK_EXTAL, 270 .clk_extal_usb_id = CLK_USB_EXTAL, 271 .pll0_div = 2, 272 .get_pll_config = r8a7790_get_pll_config, 273 }; 274 275 static const struct udevice_id r8a7790_clk_ids[] = { 276 { 277 .compatible = "renesas,r8a7790-cpg-mssr", 278 .data = (ulong)&r8a7790_cpg_mssr_info 279 }, 280 { } 281 }; 282 283 U_BOOT_DRIVER(clk_r8a7790) = { 284 .name = "clk_r8a7790", 285 .id = UCLASS_CLK, 286 .of_match = r8a7790_clk_ids, 287 .priv_auto_alloc_size = sizeof(struct gen2_clk_priv), 288 .ops = &gen2_clk_ops, 289 .probe = gen2_clk_probe, 290 .remove = gen2_clk_remove, 291 }; 292
