1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * MMCIF driver. 4 * 5 * Copyright (C) 2011 Renesas Solutions Corp. 6 */ 7 8 #include <config.h> 9 #include <common.h> 10 #include <watchdog.h> 11 #include <command.h> 12 #include <mmc.h> 13 #include <clk.h> 14 #include <dm.h> 15 #include <malloc.h> 16 #include <linux/errno.h> 17 #include <linux/compat.h> 18 #include <linux/io.h> 19 #include <linux/sizes.h> 20 #include "sh_mmcif.h" 21 22 #define DRIVER_NAME "sh_mmcif" 23 24 static int sh_mmcif_intr(void *dev_id) 25 { 26 struct sh_mmcif_host *host = dev_id; 27 u32 state = 0; 28 29 state = sh_mmcif_read(&host->regs->ce_int); 30 state &= sh_mmcif_read(&host->regs->ce_int_mask); 31 32 if (state & INT_RBSYE) { 33 sh_mmcif_write(~(INT_RBSYE | INT_CRSPE), &host->regs->ce_int); 34 sh_mmcif_bitclr(MASK_MRBSYE, &host->regs->ce_int_mask); 35 goto end; 36 } else if (state & INT_CRSPE) { 37 sh_mmcif_write(~INT_CRSPE, &host->regs->ce_int); 38 sh_mmcif_bitclr(MASK_MCRSPE, &host->regs->ce_int_mask); 39 /* one more interrupt (INT_RBSYE) */ 40 if (sh_mmcif_read(&host->regs->ce_cmd_set) & CMD_SET_RBSY) 41 return -EAGAIN; 42 goto end; 43 } else if (state & INT_BUFREN) { 44 sh_mmcif_write(~INT_BUFREN, &host->regs->ce_int); 45 sh_mmcif_bitclr(MASK_MBUFREN, &host->regs->ce_int_mask); 46 goto end; 47 } else if (state & INT_BUFWEN) { 48 sh_mmcif_write(~INT_BUFWEN, &host->regs->ce_int); 49 sh_mmcif_bitclr(MASK_MBUFWEN, &host->regs->ce_int_mask); 50 goto end; 51 } else if (state & INT_CMD12DRE) { 52 sh_mmcif_write(~(INT_CMD12DRE | INT_CMD12RBE | INT_CMD12CRE | 53 INT_BUFRE), &host->regs->ce_int); 54 sh_mmcif_bitclr(MASK_MCMD12DRE, &host->regs->ce_int_mask); 55 goto end; 56 } else if (state & INT_BUFRE) { 57 sh_mmcif_write(~INT_BUFRE, &host->regs->ce_int); 58 sh_mmcif_bitclr(MASK_MBUFRE, &host->regs->ce_int_mask); 59 goto end; 60 } else if (state & INT_DTRANE) { 61 sh_mmcif_write(~INT_DTRANE, &host->regs->ce_int); 62 sh_mmcif_bitclr(MASK_MDTRANE, &host->regs->ce_int_mask); 63 goto end; 64 } else if (state & INT_CMD12RBE) { 65 sh_mmcif_write(~(INT_CMD12RBE | INT_CMD12CRE), 66 &host->regs->ce_int); 67 sh_mmcif_bitclr(MASK_MCMD12RBE, &host->regs->ce_int_mask); 68 goto end; 69 } else if (state & INT_ERR_STS) { 70 /* err interrupts */ 71 sh_mmcif_write(~state, &host->regs->ce_int); 72 sh_mmcif_bitclr(state, &host->regs->ce_int_mask); 73 goto err; 74 } else 75 return -EAGAIN; 76 77 err: 78 host->sd_error = 1; 79 debug("%s: int err state = %08x\n", DRIVER_NAME, state); 80 end: 81 host->wait_int = 1; 82 return 0; 83 } 84 85 static int mmcif_wait_interrupt_flag(struct sh_mmcif_host *host) 86 { 87 int timeout = 10000000; 88 89 while (1) { 90 timeout--; 91 if (timeout < 0) { 92 printf("timeout\n"); 93 return 0; 94 } 95 96 if (!sh_mmcif_intr(host)) 97 break; 98 99 udelay(1); /* 1 usec */ 100 } 101 102 return 1; /* Return value: NOT 0 = complete waiting */ 103 } 104 105 static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk) 106 { 107 sh_mmcif_bitclr(CLK_ENABLE, &host->regs->ce_clk_ctrl); 108 sh_mmcif_bitclr(CLK_CLEAR, &host->regs->ce_clk_ctrl); 109 110 if (!clk) 111 return; 112 113 if (clk == CLKDEV_EMMC_DATA) 114 sh_mmcif_bitset(CLK_PCLK, &host->regs->ce_clk_ctrl); 115 else 116 sh_mmcif_bitset((fls(DIV_ROUND_UP(host->clk, 117 clk) - 1) - 1) << 16, 118 &host->regs->ce_clk_ctrl); 119 sh_mmcif_bitset(CLK_ENABLE, &host->regs->ce_clk_ctrl); 120 } 121 122 static void sh_mmcif_sync_reset(struct sh_mmcif_host *host) 123 { 124 u32 tmp; 125 126 tmp = sh_mmcif_read(&host->regs->ce_clk_ctrl) & (CLK_ENABLE | 127 CLK_CLEAR); 128 129 sh_mmcif_write(SOFT_RST_ON, &host->regs->ce_version); 130 sh_mmcif_write(SOFT_RST_OFF, &host->regs->ce_version); 131 sh_mmcif_bitset(tmp | SRSPTO_256 | SRBSYTO_29 | SRWDTO_29 | SCCSTO_29, 132 &host->regs->ce_clk_ctrl); 133 /* byte swap on */ 134 sh_mmcif_bitset(BUF_ACC_ATYP, &host->regs->ce_buf_acc); 135 } 136 137 static int sh_mmcif_error_manage(struct sh_mmcif_host *host) 138 { 139 u32 state1, state2; 140 int ret, timeout = 10000000; 141 142 host->sd_error = 0; 143 host->wait_int = 0; 144 145 state1 = sh_mmcif_read(&host->regs->ce_host_sts1); 146 state2 = sh_mmcif_read(&host->regs->ce_host_sts2); 147 debug("%s: ERR HOST_STS1 = %08x\n", \ 148 DRIVER_NAME, sh_mmcif_read(&host->regs->ce_host_sts1)); 149 debug("%s: ERR HOST_STS2 = %08x\n", \ 150 DRIVER_NAME, sh_mmcif_read(&host->regs->ce_host_sts2)); 151 152 if (state1 & STS1_CMDSEQ) { 153 debug("%s: Forced end of command sequence\n", DRIVER_NAME); 154 sh_mmcif_bitset(CMD_CTRL_BREAK, &host->regs->ce_cmd_ctrl); 155 sh_mmcif_bitset(~CMD_CTRL_BREAK, &host->regs->ce_cmd_ctrl); 156 while (1) { 157 timeout--; 158 if (timeout < 0) { 159 printf(DRIVER_NAME": Forceed end of " \ 160 "command sequence timeout err\n"); 161 return -EILSEQ; 162 } 163 if (!(sh_mmcif_read(&host->regs->ce_host_sts1) 164 & STS1_CMDSEQ)) 165 break; 166 } 167 sh_mmcif_sync_reset(host); 168 return -EILSEQ; 169 } 170 171 if (state2 & STS2_CRC_ERR) 172 ret = -EILSEQ; 173 else if (state2 & STS2_TIMEOUT_ERR) 174 ret = -ETIMEDOUT; 175 else 176 ret = -EILSEQ; 177 return ret; 178 } 179 180 static int sh_mmcif_single_read(struct sh_mmcif_host *host, 181 struct mmc_data *data) 182 { 183 long time; 184 u32 blocksize, i; 185 unsigned long *p = (unsigned long *)data->dest; 186 187 if ((unsigned long)p & 0x00000001) { 188 printf("%s: The data pointer is unaligned.", __func__); 189 return -EIO; 190 } 191 192 host->wait_int = 0; 193 194 /* buf read enable */ 195 sh_mmcif_bitset(MASK_MBUFREN, &host->regs->ce_int_mask); 196 time = mmcif_wait_interrupt_flag(host); 197 if (time == 0 || host->sd_error != 0) 198 return sh_mmcif_error_manage(host); 199 200 host->wait_int = 0; 201 blocksize = (BLOCK_SIZE_MASK & 202 sh_mmcif_read(&host->regs->ce_block_set)) + 3; 203 for (i = 0; i < blocksize / 4; i++) 204 *p++ = sh_mmcif_read(&host->regs->ce_data); 205 206 /* buffer read end */ 207 sh_mmcif_bitset(MASK_MBUFRE, &host->regs->ce_int_mask); 208 time = mmcif_wait_interrupt_flag(host); 209 if (time == 0 || host->sd_error != 0) 210 return sh_mmcif_error_manage(host); 211 212 host->wait_int = 0; 213 return 0; 214 } 215 216 static int sh_mmcif_multi_read(struct sh_mmcif_host *host, 217 struct mmc_data *data) 218 { 219 long time; 220 u32 blocksize, i, j; 221 unsigned long *p = (unsigned long *)data->dest; 222 223 if ((unsigned long)p & 0x00000001) { 224 printf("%s: The data pointer is unaligned.", __func__); 225 return -EIO; 226 } 227 228 host->wait_int = 0; 229 blocksize = BLOCK_SIZE_MASK & sh_mmcif_read(&host->regs->ce_block_set); 230 for (j = 0; j < data->blocks; j++) { 231 sh_mmcif_bitset(MASK_MBUFREN, &host->regs->ce_int_mask); 232 time = mmcif_wait_interrupt_flag(host); 233 if (time == 0 || host->sd_error != 0) 234 return sh_mmcif_error_manage(host); 235 236 host->wait_int = 0; 237 for (i = 0; i < blocksize / 4; i++) 238 *p++ = sh_mmcif_read(&host->regs->ce_data); 239 240 WATCHDOG_RESET(); 241 } 242 return 0; 243 } 244 245 static int sh_mmcif_single_write(struct sh_mmcif_host *host, 246 struct mmc_data *data) 247 { 248 long time; 249 u32 blocksize, i; 250 const unsigned long *p = (unsigned long *)data->dest; 251 252 if ((unsigned long)p & 0x00000001) { 253 printf("%s: The data pointer is unaligned.", __func__); 254 return -EIO; 255 } 256 257 host->wait_int = 0; 258 sh_mmcif_bitset(MASK_MBUFWEN, &host->regs->ce_int_mask); 259 260 time = mmcif_wait_interrupt_flag(host); 261 if (time == 0 || host->sd_error != 0) 262 return sh_mmcif_error_manage(host); 263 264 host->wait_int = 0; 265 blocksize = (BLOCK_SIZE_MASK & 266 sh_mmcif_read(&host->regs->ce_block_set)) + 3; 267 for (i = 0; i < blocksize / 4; i++) 268 sh_mmcif_write(*p++, &host->regs->ce_data); 269 270 /* buffer write end */ 271 sh_mmcif_bitset(MASK_MDTRANE, &host->regs->ce_int_mask); 272 273 time = mmcif_wait_interrupt_flag(host); 274 if (time == 0 || host->sd_error != 0) 275 return sh_mmcif_error_manage(host); 276 277 host->wait_int = 0; 278 return 0; 279 } 280 281 static int sh_mmcif_multi_write(struct sh_mmcif_host *host, 282 struct mmc_data *data) 283 { 284 long time; 285 u32 i, j, blocksize; 286 const unsigned long *p = (unsigned long *)data->dest; 287 288 if ((unsigned long)p & 0x00000001) { 289 printf("%s: The data pointer is unaligned.", __func__); 290 return -EIO; 291 } 292 293 host->wait_int = 0; 294 blocksize = BLOCK_SIZE_MASK & sh_mmcif_read(&host->regs->ce_block_set); 295 for (j = 0; j < data->blocks; j++) { 296 sh_mmcif_bitset(MASK_MBUFWEN, &host->regs->ce_int_mask); 297 298 time = mmcif_wait_interrupt_flag(host); 299 300 if (time == 0 || host->sd_error != 0) 301 return sh_mmcif_error_manage(host); 302 303 host->wait_int = 0; 304 for (i = 0; i < blocksize / 4; i++) 305 sh_mmcif_write(*p++, &host->regs->ce_data); 306 307 WATCHDOG_RESET(); 308 } 309 return 0; 310 } 311 312 static void sh_mmcif_get_response(struct sh_mmcif_host *host, 313 struct mmc_cmd *cmd) 314 { 315 if (cmd->resp_type & MMC_RSP_136) { 316 cmd->response[0] = sh_mmcif_read(&host->regs->ce_resp3); 317 cmd->response[1] = sh_mmcif_read(&host->regs->ce_resp2); 318 cmd->response[2] = sh_mmcif_read(&host->regs->ce_resp1); 319 cmd->response[3] = sh_mmcif_read(&host->regs->ce_resp0); 320 debug(" RESP %08x, %08x, %08x, %08x\n", cmd->response[0], 321 cmd->response[1], cmd->response[2], cmd->response[3]); 322 } else { 323 cmd->response[0] = sh_mmcif_read(&host->regs->ce_resp0); 324 } 325 } 326 327 static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host, 328 struct mmc_cmd *cmd) 329 { 330 cmd->response[0] = sh_mmcif_read(&host->regs->ce_resp_cmd12); 331 } 332 333 static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host, 334 struct mmc_data *data, struct mmc_cmd *cmd) 335 { 336 u32 tmp = 0; 337 u32 opc = cmd->cmdidx; 338 339 /* Response Type check */ 340 switch (cmd->resp_type) { 341 case MMC_RSP_NONE: 342 tmp |= CMD_SET_RTYP_NO; 343 break; 344 case MMC_RSP_R1: 345 case MMC_RSP_R1b: 346 case MMC_RSP_R3: 347 tmp |= CMD_SET_RTYP_6B; 348 break; 349 case MMC_RSP_R2: 350 tmp |= CMD_SET_RTYP_17B; 351 break; 352 default: 353 printf(DRIVER_NAME": Not support type response.\n"); 354 break; 355 } 356 357 /* RBSY */ 358 if (opc == MMC_CMD_SWITCH) 359 tmp |= CMD_SET_RBSY; 360 361 /* WDAT / DATW */ 362 if (host->data) { 363 tmp |= CMD_SET_WDAT; 364 switch (host->bus_width) { 365 case MMC_BUS_WIDTH_1: 366 tmp |= CMD_SET_DATW_1; 367 break; 368 case MMC_BUS_WIDTH_4: 369 tmp |= CMD_SET_DATW_4; 370 break; 371 case MMC_BUS_WIDTH_8: 372 tmp |= CMD_SET_DATW_8; 373 break; 374 default: 375 printf(DRIVER_NAME": Not support bus width.\n"); 376 break; 377 } 378 } 379 /* DWEN */ 380 if (opc == MMC_CMD_WRITE_SINGLE_BLOCK || 381 opc == MMC_CMD_WRITE_MULTIPLE_BLOCK) 382 tmp |= CMD_SET_DWEN; 383 /* CMLTE/CMD12EN */ 384 if (opc == MMC_CMD_READ_MULTIPLE_BLOCK || 385 opc == MMC_CMD_WRITE_MULTIPLE_BLOCK) { 386 tmp |= CMD_SET_CMLTE | CMD_SET_CMD12EN; 387 sh_mmcif_bitset(data->blocks << 16, &host->regs->ce_block_set); 388 } 389 /* RIDXC[1:0] check bits */ 390 if (opc == MMC_CMD_SEND_OP_COND || opc == MMC_CMD_ALL_SEND_CID || 391 opc == MMC_CMD_SEND_CSD || opc == MMC_CMD_SEND_CID) 392 tmp |= CMD_SET_RIDXC_BITS; 393 /* RCRC7C[1:0] check bits */ 394 if (opc == MMC_CMD_SEND_OP_COND) 395 tmp |= CMD_SET_CRC7C_BITS; 396 /* RCRC7C[1:0] internal CRC7 */ 397 if (opc == MMC_CMD_ALL_SEND_CID || 398 opc == MMC_CMD_SEND_CSD || opc == MMC_CMD_SEND_CID) 399 tmp |= CMD_SET_CRC7C_INTERNAL; 400 401 return opc = ((opc << 24) | tmp); 402 } 403 404 static u32 sh_mmcif_data_trans(struct sh_mmcif_host *host, 405 struct mmc_data *data, u16 opc) 406 { 407 u32 ret; 408 409 switch (opc) { 410 case MMC_CMD_READ_MULTIPLE_BLOCK: 411 ret = sh_mmcif_multi_read(host, data); 412 break; 413 case MMC_CMD_WRITE_MULTIPLE_BLOCK: 414 ret = sh_mmcif_multi_write(host, data); 415 break; 416 case MMC_CMD_WRITE_SINGLE_BLOCK: 417 ret = sh_mmcif_single_write(host, data); 418 break; 419 case MMC_CMD_READ_SINGLE_BLOCK: 420 case MMC_CMD_SEND_EXT_CSD: 421 ret = sh_mmcif_single_read(host, data); 422 break; 423 default: 424 printf(DRIVER_NAME": NOT SUPPORT CMD = d'%08d\n", opc); 425 ret = -EINVAL; 426 break; 427 } 428 return ret; 429 } 430 431 static int sh_mmcif_start_cmd(struct sh_mmcif_host *host, 432 struct mmc_data *data, struct mmc_cmd *cmd) 433 { 434 long time; 435 int ret = 0, mask = 0; 436 u32 opc = cmd->cmdidx; 437 438 if (opc == MMC_CMD_STOP_TRANSMISSION) { 439 /* MMCIF sends the STOP command automatically */ 440 if (host->last_cmd == MMC_CMD_READ_MULTIPLE_BLOCK) 441 sh_mmcif_bitset(MASK_MCMD12DRE, 442 &host->regs->ce_int_mask); 443 else 444 sh_mmcif_bitset(MASK_MCMD12RBE, 445 &host->regs->ce_int_mask); 446 447 time = mmcif_wait_interrupt_flag(host); 448 if (time == 0 || host->sd_error != 0) 449 return sh_mmcif_error_manage(host); 450 451 sh_mmcif_get_cmd12response(host, cmd); 452 return 0; 453 } 454 if (opc == MMC_CMD_SWITCH) 455 mask = MASK_MRBSYE; 456 else 457 mask = MASK_MCRSPE; 458 459 mask |= MASK_MCMDVIO | MASK_MBUFVIO | MASK_MWDATERR | 460 MASK_MRDATERR | MASK_MRIDXERR | MASK_MRSPERR | 461 MASK_MCCSTO | MASK_MCRCSTO | MASK_MWDATTO | 462 MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO; 463 464 if (host->data) { 465 sh_mmcif_write(0, &host->regs->ce_block_set); 466 sh_mmcif_write(data->blocksize, &host->regs->ce_block_set); 467 } 468 opc = sh_mmcif_set_cmd(host, data, cmd); 469 470 sh_mmcif_write(INT_START_MAGIC, &host->regs->ce_int); 471 sh_mmcif_write(mask, &host->regs->ce_int_mask); 472 473 debug("CMD%d ARG:%08x\n", cmd->cmdidx, cmd->cmdarg); 474 /* set arg */ 475 sh_mmcif_write(cmd->cmdarg, &host->regs->ce_arg); 476 host->wait_int = 0; 477 /* set cmd */ 478 sh_mmcif_write(opc, &host->regs->ce_cmd_set); 479 480 time = mmcif_wait_interrupt_flag(host); 481 if (time == 0) 482 return sh_mmcif_error_manage(host); 483 484 if (host->sd_error) { 485 switch (cmd->cmdidx) { 486 case MMC_CMD_ALL_SEND_CID: 487 case MMC_CMD_SELECT_CARD: 488 case MMC_CMD_APP_CMD: 489 ret = -ETIMEDOUT; 490 break; 491 default: 492 printf(DRIVER_NAME": Cmd(d'%d) err\n", cmd->cmdidx); 493 ret = sh_mmcif_error_manage(host); 494 break; 495 } 496 host->sd_error = 0; 497 host->wait_int = 0; 498 return ret; 499 } 500 501 /* if no response */ 502 if (!(opc & 0x00C00000)) 503 return 0; 504 505 if (host->wait_int == 1) { 506 sh_mmcif_get_response(host, cmd); 507 host->wait_int = 0; 508 } 509 if (host->data) 510 ret = sh_mmcif_data_trans(host, data, cmd->cmdidx); 511 host->last_cmd = cmd->cmdidx; 512 513 return ret; 514 } 515 516 static int sh_mmcif_send_cmd_common(struct sh_mmcif_host *host, 517 struct mmc_cmd *cmd, struct mmc_data *data) 518 { 519 int ret; 520 521 WATCHDOG_RESET(); 522 523 switch (cmd->cmdidx) { 524 case MMC_CMD_APP_CMD: 525 return -ETIMEDOUT; 526 case MMC_CMD_SEND_EXT_CSD: /* = SD_SEND_IF_COND (8) */ 527 if (data) 528 /* ext_csd */ 529 break; 530 else 531 /* send_if_cond cmd (not support) */ 532 return -ETIMEDOUT; 533 default: 534 break; 535 } 536 host->sd_error = 0; 537 host->data = data; 538 ret = sh_mmcif_start_cmd(host, data, cmd); 539 host->data = NULL; 540 541 return ret; 542 } 543 544 static int sh_mmcif_set_ios_common(struct sh_mmcif_host *host, struct mmc *mmc) 545 { 546 if (mmc->clock) 547 sh_mmcif_clock_control(host, mmc->clock); 548 549 if (mmc->bus_width == 8) 550 host->bus_width = MMC_BUS_WIDTH_8; 551 else if (mmc->bus_width == 4) 552 host->bus_width = MMC_BUS_WIDTH_4; 553 else 554 host->bus_width = MMC_BUS_WIDTH_1; 555 556 debug("clock = %d, buswidth = %d\n", mmc->clock, mmc->bus_width); 557 558 return 0; 559 } 560 561 static int sh_mmcif_initialize_common(struct sh_mmcif_host *host) 562 { 563 sh_mmcif_sync_reset(host); 564 sh_mmcif_write(MASK_ALL, &host->regs->ce_int_mask); 565 return 0; 566 } 567 568 #ifndef CONFIG_DM_MMC 569 static void *mmc_priv(struct mmc *mmc) 570 { 571 return (void *)mmc->priv; 572 } 573 574 static int sh_mmcif_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, 575 struct mmc_data *data) 576 { 577 struct sh_mmcif_host *host = mmc_priv(mmc); 578 579 return sh_mmcif_send_cmd_common(host, cmd, data); 580 } 581 582 static int sh_mmcif_set_ios(struct mmc *mmc) 583 { 584 struct sh_mmcif_host *host = mmc_priv(mmc); 585 586 return sh_mmcif_set_ios_common(host, mmc); 587 } 588 589 static int sh_mmcif_initialize(struct mmc *mmc) 590 { 591 struct sh_mmcif_host *host = mmc_priv(mmc); 592 593 return sh_mmcif_initialize_common(host); 594 } 595 596 static const struct mmc_ops sh_mmcif_ops = { 597 .send_cmd = sh_mmcif_send_cmd, 598 .set_ios = sh_mmcif_set_ios, 599 .init = sh_mmcif_initialize, 600 }; 601 602 static struct mmc_config sh_mmcif_cfg = { 603 .name = DRIVER_NAME, 604 .ops = &sh_mmcif_ops, 605 .host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT | 606 MMC_MODE_8BIT, 607 .voltages = MMC_VDD_32_33 | MMC_VDD_33_34, 608 .b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT, 609 }; 610 611 int mmcif_mmc_init(void) 612 { 613 struct mmc *mmc; 614 struct sh_mmcif_host *host = NULL; 615 616 host = malloc(sizeof(struct sh_mmcif_host)); 617 if (!host) 618 return -ENOMEM; 619 memset(host, 0, sizeof(*host)); 620 621 host->regs = (struct sh_mmcif_regs *)CONFIG_SH_MMCIF_ADDR; 622 host->clk = CONFIG_SH_MMCIF_CLK; 623 624 sh_mmcif_cfg.f_min = MMC_CLK_DIV_MIN(host->clk); 625 sh_mmcif_cfg.f_max = MMC_CLK_DIV_MAX(host->clk); 626 627 mmc = mmc_create(&sh_mmcif_cfg, host); 628 if (mmc == NULL) { 629 free(host); 630 return -ENOMEM; 631 } 632 633 return 0; 634 } 635 636 #else 637 struct sh_mmcif_plat { 638 struct mmc_config cfg; 639 struct mmc mmc; 640 }; 641 642 int sh_mmcif_dm_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, 643 struct mmc_data *data) 644 { 645 struct sh_mmcif_host *host = dev_get_priv(dev); 646 647 return sh_mmcif_send_cmd_common(host, cmd, data); 648 } 649 650 int sh_mmcif_dm_set_ios(struct udevice *dev) 651 { 652 struct sh_mmcif_host *host = dev_get_priv(dev); 653 struct mmc *mmc = mmc_get_mmc_dev(dev); 654 655 return sh_mmcif_set_ios_common(host, mmc); 656 } 657 658 static const struct dm_mmc_ops sh_mmcif_dm_ops = { 659 .send_cmd = sh_mmcif_dm_send_cmd, 660 .set_ios = sh_mmcif_dm_set_ios, 661 }; 662 663 static int sh_mmcif_dm_bind(struct udevice *dev) 664 { 665 struct sh_mmcif_plat *plat = dev_get_platdata(dev); 666 667 return mmc_bind(dev, &plat->mmc, &plat->cfg); 668 } 669 670 static int sh_mmcif_dm_probe(struct udevice *dev) 671 { 672 struct sh_mmcif_plat *plat = dev_get_platdata(dev); 673 struct sh_mmcif_host *host = dev_get_priv(dev); 674 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); 675 struct clk sh_mmcif_clk; 676 fdt_addr_t base; 677 int ret; 678 679 base = devfdt_get_addr(dev); 680 if (base == FDT_ADDR_T_NONE) 681 return -EINVAL; 682 683 host->regs = (struct sh_mmcif_regs *)devm_ioremap(dev, base, SZ_2K); 684 if (!host->regs) 685 return -ENOMEM; 686 687 ret = clk_get_by_index(dev, 0, &sh_mmcif_clk); 688 if (ret) { 689 debug("failed to get clock, ret=%d\n", ret); 690 return ret; 691 } 692 693 ret = clk_enable(&sh_mmcif_clk); 694 if (ret) { 695 debug("failed to enable clock, ret=%d\n", ret); 696 return ret; 697 } 698 699 host->clk = clk_get_rate(&sh_mmcif_clk); 700 701 plat->cfg.name = dev->name; 702 plat->cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS; 703 704 switch (fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "bus-width", 705 1)) { 706 case 8: 707 plat->cfg.host_caps |= MMC_MODE_8BIT; 708 break; 709 case 4: 710 plat->cfg.host_caps |= MMC_MODE_4BIT; 711 break; 712 case 1: 713 break; 714 default: 715 dev_err(dev, "Invalid \"bus-width\" value\n"); 716 return -EINVAL; 717 } 718 719 sh_mmcif_initialize_common(host); 720 721 plat->cfg.voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34; 722 plat->cfg.f_min = MMC_CLK_DIV_MIN(host->clk); 723 plat->cfg.f_max = MMC_CLK_DIV_MAX(host->clk); 724 plat->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; 725 726 upriv->mmc = &plat->mmc; 727 728 return 0; 729 } 730 731 static const struct udevice_id sh_mmcif_sd_match[] = { 732 { .compatible = "renesas,sh-mmcif" }, 733 { /* sentinel */ } 734 }; 735 736 U_BOOT_DRIVER(sh_mmcif_mmc) = { 737 .name = "sh-mmcif", 738 .id = UCLASS_MMC, 739 .of_match = sh_mmcif_sd_match, 740 .bind = sh_mmcif_dm_bind, 741 .probe = sh_mmcif_dm_probe, 742 .priv_auto_alloc_size = sizeof(struct sh_mmcif_host), 743 .platdata_auto_alloc_size = sizeof(struct sh_mmcif_plat), 744 .ops = &sh_mmcif_dm_ops, 745 }; 746 #endif 747
