1 /* 2 * Dave Ethernet Controller driver 3 * 4 * Copyright (C) 2008 Dave S.r.l. <www.dave.eu> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #ifndef __DRIVERS_DNET_H__ 12 #define __DRIVERS_DNET_H__ 13 14 #define DRIVERNAME "dnet" 15 16 struct dnet_registers { 17 /* ALL DNET FIFO REGISTERS */ 18 u32 RX_LEN_FIFO; 19 u32 RX_DATA_FIFO; 20 u32 TX_LEN_FIFO; 21 u32 TX_DATA_FIFO; 22 u32 pad1[0x3c]; 23 /* ALL DNET CONTROL/STATUS REGISTERS */ 24 u32 VERCAPS; 25 u32 INTR_SRC; 26 u32 INTR_ENB; 27 u32 RX_STATUS; 28 u32 TX_STATUS; 29 u32 RX_FRAMES_CNT; 30 u32 TX_FRAMES_CNT; 31 u32 RX_FIFO_TH; 32 u32 TX_FIFO_TH; 33 u32 SYS_CTL; 34 u32 PAUSE_TMR; 35 u32 RX_FIFO_WCNT; 36 u32 TX_FIFO_WCNT; 37 u32 pad2[0x33]; 38 /* ALL DNET MAC REGISTERS */ 39 u32 MACREG_DATA; /* Mac-Reg Data */ 40 u32 MACREG_ADDR; /* Mac-Reg Addr */ 41 u32 pad3[0x3e]; 42 /* ALL DNET RX STATISTICS COUNTERS */ 43 u32 RX_PKT_IGNR_CNT; 44 u32 RX_LEN_CHK_ERR_CNT; 45 u32 RX_LNG_FRM_CNT; 46 u32 RX_SHRT_FRM_CNT; 47 u32 RX_IPG_VIOL_CNT; 48 u32 RX_CRC_ERR_CNT; 49 u32 RX_OK_PKT_CNT; 50 u32 RX_CTL_FRM_CNT; 51 u32 RX_PAUSE_FRM_CNT; 52 u32 RX_MULTICAST_CNT; 53 u32 RX_BROADCAST_CNT; 54 u32 RX_VLAN_TAG_CNT; 55 u32 RX_PRE_SHRINK_CNT; 56 u32 RX_DRIB_NIB_CNT; 57 u32 RX_UNSUP_OPCD_CNT; 58 u32 RX_BYTE_CNT; 59 u32 pad4[0x30]; 60 /* DNET TX STATISTICS COUNTERS */ 61 u32 TX_UNICAST_CNT; 62 u32 TX_PAUSE_FRM_CNT; 63 u32 TX_MULTICAST_CNT; 64 u32 TX_BRDCAST_CNT; 65 u32 TX_VLAN_TAG_CNT; 66 u32 TX_BAD_FCS_CNT; 67 u32 TX_JUMBO_CNT; 68 u32 TX_BYTE_CNT; 69 }; 70 71 /* SOME INTERNAL MAC-CORE REGISTER */ 72 #define DNET_INTERNAL_MODE_REG 0x0 73 #define DNET_INTERNAL_RXTX_CONTROL_REG 0x2 74 #define DNET_INTERNAL_MAX_PKT_SIZE_REG 0x4 75 #define DNET_INTERNAL_IGP_REG 0x8 76 #define DNET_INTERNAL_MAC_ADDR_0_REG 0xa 77 #define DNET_INTERNAL_MAC_ADDR_1_REG 0xc 78 #define DNET_INTERNAL_MAC_ADDR_2_REG 0xe 79 #define DNET_INTERNAL_TX_RX_STS_REG 0x12 80 #define DNET_INTERNAL_GMII_MNG_CTL_REG 0x14 81 #define DNET_INTERNAL_GMII_MNG_DAT_REG 0x16 82 83 #define DNET_INTERNAL_GMII_MNG_CMD_FIN (1 << 14) 84 85 #define DNET_INTERNAL_WRITE (1 << 31) 86 87 /* MAC-CORE REGISTER FIELDS */ 88 89 /* MAC-CORE MODE REGISTER FIELDS */ 90 #define DNET_INTERNAL_MODE_GBITEN (1 << 0) 91 #define DNET_INTERNAL_MODE_FCEN (1 << 1) 92 #define DNET_INTERNAL_MODE_RXEN (1 << 2) 93 #define DNET_INTERNAL_MODE_TXEN (1 << 3) 94 95 /* MAC-CORE RXTX CONTROL REGISTER FIELDS */ 96 #define DNET_INTERNAL_RXTX_CONTROL_RXSHORTFRAME (1 << 8) 97 #define DNET_INTERNAL_RXTX_CONTROL_RXBROADCAST (1 << 7) 98 #define DNET_INTERNAL_RXTX_CONTROL_RXMULTICAST (1 << 4) 99 #define DNET_INTERNAL_RXTX_CONTROL_RXPAUSE (1 << 3) 100 #define DNET_INTERNAL_RXTX_CONTROL_DISTXFCS (1 << 2) 101 #define DNET_INTERNAL_RXTX_CONTROL_DISCFXFCS (1 << 1) 102 #define DNET_INTERNAL_RXTX_CONTROL_ENPROMISC (1 << 0) 103 #define DNET_INTERNAL_RXTX_CONTROL_DROPCONTROL (1 << 6) 104 #define DNET_INTERNAL_RXTX_CONTROL_ENABLEHALFDUP (1 << 5) 105 106 /* SYSTEM CONTROL REGISTER FIELDS */ 107 #define DNET_SYS_CTL_IGNORENEXTPKT (1 << 0) 108 #define DNET_SYS_CTL_SENDPAUSE (1 << 2) 109 #define DNET_SYS_CTL_RXFIFOFLUSH (1 << 3) 110 #define DNET_SYS_CTL_TXFIFOFLUSH (1 << 4) 111 112 /* TX STATUS REGISTER FIELDS */ 113 #define DNET_TX_STATUS_FIFO_ALMOST_EMPTY (1 << 2) 114 #define DNET_TX_STATUS_FIFO_ALMOST_FULL (1 << 1) 115 116 /* INTERRUPT SOURCE REGISTER FIELDS */ 117 #define DNET_INTR_SRC_TX_PKTSENT (1 << 0) 118 #define DNET_INTR_SRC_TX_FIFOAF (1 << 1) 119 #define DNET_INTR_SRC_TX_FIFOAE (1 << 2) 120 #define DNET_INTR_SRC_TX_DISCFRM (1 << 3) 121 #define DNET_INTR_SRC_TX_FIFOFULL (1 << 4) 122 #define DNET_INTR_SRC_RX_CMDFIFOAF (1 << 8) 123 #define DNET_INTR_SRC_RX_CMDFIFOFF (1 << 9) 124 #define DNET_INTR_SRC_RX_DATAFIFOFF (1 << 10) 125 #define DNET_INTR_SRC_TX_SUMMARY (1 << 16) 126 #define DNET_INTR_SRC_RX_SUMMARY (1 << 17) 127 #define DNET_INTR_SRC_PHY (1 << 19) 128 129 /* INTERRUPT ENABLE REGISTER FIELDS */ 130 #define DNET_INTR_ENB_TX_PKTSENT (1 << 0) 131 #define DNET_INTR_ENB_TX_FIFOAF (1 << 1) 132 #define DNET_INTR_ENB_TX_FIFOAE (1 << 2) 133 #define DNET_INTR_ENB_TX_DISCFRM (1 << 3) 134 #define DNET_INTR_ENB_TX_FIFOFULL (1 << 4) 135 #define DNET_INTR_ENB_RX_PKTRDY (1 << 8) 136 #define DNET_INTR_ENB_RX_FIFOAF (1 << 9) 137 #define DNET_INTR_ENB_RX_FIFOERR (1 << 10) 138 #define DNET_INTR_ENB_RX_ERROR (1 << 11) 139 #define DNET_INTR_ENB_RX_FIFOFULL (1 << 12) 140 #define DNET_INTR_ENB_RX_FIFOAE (1 << 13) 141 #define DNET_INTR_ENB_TX_SUMMARY (1 << 16) 142 #define DNET_INTR_ENB_RX_SUMMARY (1 << 17) 143 #define DNET_INTR_ENB_GLOBAL_ENABLE (1 << 18) 144 145 /* 146 * Capabilities. Used by the driver to know the capabilities that 147 * the ethernet controller inside the FPGA have. 148 */ 149 150 #define DNET_HAS_MDIO (1 << 0) 151 #define DNET_HAS_IRQ (1 << 1) 152 #define DNET_HAS_GIGABIT (1 << 2) 153 #define DNET_HAS_DMA (1 << 3) 154 155 #define DNET_HAS_MII (1 << 4) /* or GMII */ 156 #define DNET_HAS_RMII (1 << 5) /* or RGMII */ 157 158 #define DNET_CAPS_MASK 0xFFFF 159 160 #define DNET_FIFO_SIZE 2048 /* 2K x 32 bit */ 161 #define DNET_FIFO_TX_DATA_AF_TH (DNET_FIFO_SIZE - 384) /* 384 = 1536 / 4 */ 162 #define DNET_FIFO_TX_DATA_AE_TH (384) 163 164 #define DNET_FIFO_RX_CMD_AF_TH (1 << 16) /* just one frame inside the FIFO */ 165 166 #endif 167
