1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2012 Freescale Semiconductor, Inc. 4 * Roy Zang <tie-fei.zang (at) freescale.com> 5 */ 6 7 /* MAXFRM - maximum frame length */ 8 #define MAXFRM_MASK 0x0000ffff 9 10 #include <common.h> 11 #include <phy.h> 12 #include <asm/types.h> 13 #include <asm/io.h> 14 #include <fsl_memac.h> 15 16 #include "fm.h" 17 18 static void memac_init_mac(struct fsl_enet_mac *mac) 19 { 20 struct memac *regs = mac->base; 21 22 /* mask all interrupt */ 23 out_be32(®s->imask, IMASK_MASK_ALL); 24 25 /* clear all events */ 26 out_be32(®s->ievent, IEVENT_CLEAR_ALL); 27 28 /* set the max receive length */ 29 out_be32(®s->maxfrm, mac->max_rx_len & MAXFRM_MASK); 30 31 /* multicast frame reception for the hash entry disable */ 32 out_be32(®s->hashtable_ctrl, 0); 33 } 34 35 static void memac_enable_mac(struct fsl_enet_mac *mac) 36 { 37 struct memac *regs = mac->base; 38 39 setbits_be32(®s->command_config, 40 MEMAC_CMD_CFG_RXTX_EN | MEMAC_CMD_CFG_NO_LEN_CHK); 41 } 42 43 static void memac_disable_mac(struct fsl_enet_mac *mac) 44 { 45 struct memac *regs = mac->base; 46 47 clrbits_be32(®s->command_config, MEMAC_CMD_CFG_RXTX_EN); 48 } 49 50 static void memac_set_mac_addr(struct fsl_enet_mac *mac, u8 *mac_addr) 51 { 52 struct memac *regs = mac->base; 53 u32 mac_addr0, mac_addr1; 54 55 /* 56 * if a station address of 0x12345678ABCD, perform a write to 57 * MAC_ADDR0 of 0x78563412, MAC_ADDR1 of 0x0000CDAB 58 */ 59 mac_addr0 = (mac_addr[3] << 24) | (mac_addr[2] << 16) | \ 60 (mac_addr[1] << 8) | (mac_addr[0]); 61 out_be32(®s->mac_addr_0, mac_addr0); 62 63 mac_addr1 = ((mac_addr[5] << 8) | mac_addr[4]) & 0x0000ffff; 64 out_be32(®s->mac_addr_1, mac_addr1); 65 } 66 67 static void memac_set_interface_mode(struct fsl_enet_mac *mac, 68 phy_interface_t type, int speed) 69 { 70 /* Roy need more work here */ 71 72 struct memac *regs = mac->base; 73 u32 if_mode, if_status; 74 75 /* clear all bits relative with interface mode */ 76 if_mode = in_be32(®s->if_mode); 77 if_status = in_be32(®s->if_status); 78 79 /* set interface mode */ 80 switch (type) { 81 case PHY_INTERFACE_MODE_GMII: 82 if_mode &= ~IF_MODE_MASK; 83 if_mode |= IF_MODE_GMII; 84 break; 85 case PHY_INTERFACE_MODE_RGMII: 86 case PHY_INTERFACE_MODE_RGMII_TXID: 87 if_mode |= (IF_MODE_GMII | IF_MODE_RG); 88 break; 89 case PHY_INTERFACE_MODE_RMII: 90 if_mode |= (IF_MODE_GMII | IF_MODE_RM); 91 break; 92 case PHY_INTERFACE_MODE_SGMII: 93 case PHY_INTERFACE_MODE_SGMII_2500: 94 case PHY_INTERFACE_MODE_QSGMII: 95 if_mode &= ~IF_MODE_MASK; 96 if_mode |= (IF_MODE_GMII); 97 break; 98 case PHY_INTERFACE_MODE_XGMII: 99 if_mode &= ~IF_MODE_MASK; 100 if_mode |= IF_MODE_XGMII; 101 break; 102 default: 103 break; 104 } 105 /* Enable automatic speed selection for Non-XGMII */ 106 if (type != PHY_INTERFACE_MODE_XGMII) 107 if_mode |= IF_MODE_EN_AUTO; 108 109 if (type == PHY_INTERFACE_MODE_RGMII || 110 type == PHY_INTERFACE_MODE_RGMII_TXID) { 111 if_mode &= ~IF_MODE_EN_AUTO; 112 if_mode &= ~IF_MODE_SETSP_MASK; 113 switch (speed) { 114 case SPEED_1000: 115 if_mode |= IF_MODE_SETSP_1000M; 116 break; 117 case SPEED_100: 118 if_mode |= IF_MODE_SETSP_100M; 119 break; 120 case SPEED_10: 121 if_mode |= IF_MODE_SETSP_10M; 122 default: 123 break; 124 } 125 } 126 127 debug(" %s, if_mode = %x\n", __func__, if_mode); 128 debug(" %s, if_status = %x\n", __func__, if_status); 129 out_be32(®s->if_mode, if_mode); 130 return; 131 } 132 133 void init_memac(struct fsl_enet_mac *mac, void *base, 134 void *phyregs, int max_rx_len) 135 { 136 mac->base = base; 137 mac->phyregs = phyregs; 138 mac->max_rx_len = max_rx_len; 139 mac->init_mac = memac_init_mac; 140 mac->enable_mac = memac_enable_mac; 141 mac->disable_mac = memac_disable_mac; 142 mac->set_mac_addr = memac_set_mac_addr; 143 mac->set_if_mode = memac_set_interface_mode; 144 } 145
