1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2011 Freescale Semiconductor, Inc. 4 */ 5 #include <common.h> 6 #include <phy.h> 7 #include <fm_eth.h> 8 #include <asm/io.h> 9 #include <asm/immap_85xx.h> 10 #include <asm/fsl_serdes.h> 11 12 u32 port_to_devdisr[] = { 13 [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1, 14 [FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2, 15 [FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3, 16 [FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4, 17 [FM1_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC1_5, 18 [FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1, 19 [FM2_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC2_1, 20 [FM2_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC2_2, 21 [FM2_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC2_3, 22 [FM2_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC2_4, 23 [FM2_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC2_5, 24 [FM2_10GEC1] = FSL_CORENET_DEVDISR2_10GEC2, 25 }; 26 27 static int is_device_disabled(enum fm_port port) 28 { 29 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 30 u32 devdisr2 = in_be32(&gur->devdisr2); 31 32 return port_to_devdisr[port] & devdisr2; 33 } 34 35 void fman_disable_port(enum fm_port port) 36 { 37 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 38 39 /* don't allow disabling of DTSEC1 as its needed for MDIO */ 40 if (port == FM1_DTSEC1) 41 return; 42 43 setbits_be32(&gur->devdisr2, port_to_devdisr[port]); 44 } 45 46 void fman_enable_port(enum fm_port port) 47 { 48 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 49 50 clrbits_be32(&gur->devdisr2, port_to_devdisr[port]); 51 } 52 53 phy_interface_t fman_port_enet_if(enum fm_port port) 54 { 55 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 56 u32 rcwsr11 = in_be32(&gur->rcwsr[11]); 57 58 if (is_device_disabled(port)) 59 return PHY_INTERFACE_MODE_NONE; 60 61 if ((port == FM1_10GEC1) && (is_serdes_configured(XAUI_FM1))) 62 return PHY_INTERFACE_MODE_XGMII; 63 64 if ((port == FM2_10GEC1) && (is_serdes_configured(XAUI_FM2))) 65 return PHY_INTERFACE_MODE_XGMII; 66 67 /* handle RGMII first */ 68 if ((port == FM1_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) == 69 FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_RGMII)) 70 return PHY_INTERFACE_MODE_RGMII; 71 72 if ((port == FM1_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) == 73 FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_MII)) 74 return PHY_INTERFACE_MODE_MII; 75 76 if ((port == FM2_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) == 77 FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_RGMII)) 78 return PHY_INTERFACE_MODE_RGMII; 79 80 if ((port == FM2_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) == 81 FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII)) 82 return PHY_INTERFACE_MODE_MII; 83 84 switch (port) { 85 case FM1_DTSEC1: 86 case FM1_DTSEC2: 87 case FM1_DTSEC3: 88 case FM1_DTSEC4: 89 case FM1_DTSEC5: 90 if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1)) 91 return PHY_INTERFACE_MODE_SGMII; 92 break; 93 case FM2_DTSEC1: 94 case FM2_DTSEC2: 95 case FM2_DTSEC3: 96 case FM2_DTSEC4: 97 case FM2_DTSEC5: 98 if (is_serdes_configured(SGMII_FM2_DTSEC1 + port - FM2_DTSEC1)) 99 return PHY_INTERFACE_MODE_SGMII; 100 break; 101 default: 102 return PHY_INTERFACE_MODE_NONE; 103 } 104 105 return PHY_INTERFACE_MODE_NONE; 106 } 107
