1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Atheros PHY drivers 4 * 5 * Copyright 2011, 2013 Freescale Semiconductor, Inc. 6 * author Andy Fleming 7 */ 8 #include <phy.h> 9 10 #define AR803x_PHY_DEBUG_ADDR_REG 0x1d 11 #define AR803x_PHY_DEBUG_DATA_REG 0x1e 12 13 #define AR803x_DEBUG_REG_5 0x5 14 #define AR803x_RGMII_TX_CLK_DLY 0x100 15 16 #define AR803x_DEBUG_REG_0 0x0 17 #define AR803x_RGMII_RX_CLK_DLY 0x8000 18 19 static int ar8021_config(struct phy_device *phydev) 20 { 21 phy_write(phydev, MDIO_DEVAD_NONE, 0x00, 0x1200); 22 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); 23 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47); 24 25 phydev->supported = phydev->drv->features; 26 return 0; 27 } 28 29 static int ar8031_config(struct phy_device *phydev) 30 { 31 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID || 32 phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) { 33 phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG, 34 AR803x_DEBUG_REG_5); 35 phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG, 36 AR803x_RGMII_TX_CLK_DLY); 37 } 38 39 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID || 40 phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) { 41 phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG, 42 AR803x_DEBUG_REG_0); 43 phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG, 44 AR803x_RGMII_RX_CLK_DLY); 45 } 46 47 phydev->supported = phydev->drv->features; 48 49 genphy_config_aneg(phydev); 50 genphy_restart_aneg(phydev); 51 52 return 0; 53 } 54 55 static int ar8035_config(struct phy_device *phydev) 56 { 57 int regval; 58 59 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x0007); 60 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); 61 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); 62 regval = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); 63 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, (regval|0x0018)); 64 65 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); 66 regval = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); 67 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, (regval|0x0100)); 68 69 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) || 70 (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) { 71 /* select debug reg 5 */ 72 phy_write(phydev, MDIO_DEVAD_NONE, 0x1D, 0x5); 73 /* enable tx delay */ 74 phy_write(phydev, MDIO_DEVAD_NONE, 0x1E, 0x0100); 75 } 76 77 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) || 78 (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)) { 79 /* select debug reg 0 */ 80 phy_write(phydev, MDIO_DEVAD_NONE, 0x1D, 0x0); 81 /* enable rx delay */ 82 phy_write(phydev, MDIO_DEVAD_NONE, 0x1E, 0x8000); 83 } 84 85 phydev->supported = phydev->drv->features; 86 87 genphy_config_aneg(phydev); 88 genphy_restart_aneg(phydev); 89 90 return 0; 91 } 92 93 static struct phy_driver AR8021_driver = { 94 .name = "AR8021", 95 .uid = 0x4dd040, 96 .mask = 0x4ffff0, 97 .features = PHY_GBIT_FEATURES, 98 .config = ar8021_config, 99 .startup = genphy_startup, 100 .shutdown = genphy_shutdown, 101 }; 102 103 static struct phy_driver AR8031_driver = { 104 .name = "AR8031/AR8033", 105 .uid = 0x4dd074, 106 .mask = 0xffffffef, 107 .features = PHY_GBIT_FEATURES, 108 .config = ar8031_config, 109 .startup = genphy_startup, 110 .shutdown = genphy_shutdown, 111 }; 112 113 static struct phy_driver AR8035_driver = { 114 .name = "AR8035", 115 .uid = 0x4dd072, 116 .mask = 0xffffffef, 117 .features = PHY_GBIT_FEATURES, 118 .config = ar8035_config, 119 .startup = genphy_startup, 120 .shutdown = genphy_shutdown, 121 }; 122 123 int phy_atheros_init(void) 124 { 125 phy_register(&AR8021_driver); 126 phy_register(&AR8031_driver); 127 phy_register(&AR8035_driver); 128 129 return 0; 130 } 131
