1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Cortina CS4315/CS4340 10G PHY drivers 4 * 5 * Copyright 2014 Freescale Semiconductor, Inc. 6 * Copyright 2018 NXP 7 * 8 */ 9 10 #include <config.h> 11 #include <common.h> 12 #include <malloc.h> 13 #include <linux/ctype.h> 14 #include <linux/string.h> 15 #include <linux/err.h> 16 #include <phy.h> 17 #include <cortina.h> 18 #ifdef CONFIG_SYS_CORTINA_FW_IN_NAND 19 #include <nand.h> 20 #elif defined(CONFIG_SYS_CORTINA_FW_IN_SPIFLASH) 21 #include <spi_flash.h> 22 #elif defined(CONFIG_SYS_CORTINA_FW_IN_MMC) 23 #include <mmc.h> 24 #endif 25 26 #ifndef CONFIG_PHYLIB_10G 27 #error The Cortina PHY needs 10G support 28 #endif 29 30 #ifndef CORTINA_NO_FW_UPLOAD 31 struct cortina_reg_config cortina_reg_cfg[] = { 32 /* CS4315_enable_sr_mode */ 33 {VILLA_GLOBAL_MSEQCLKCTRL, 0x8004}, 34 {VILLA_MSEQ_OPTIONS, 0xf}, 35 {VILLA_MSEQ_PC, 0x0}, 36 {VILLA_MSEQ_BANKSELECT, 0x4}, 37 {VILLA_LINE_SDS_COMMON_SRX0_RX_CPA, 0x55}, 38 {VILLA_LINE_SDS_COMMON_SRX0_RX_LOOP_FILTER, 0x30}, 39 {VILLA_DSP_SDS_SERDES_SRX_DFE0_SELECT, 0x1}, 40 {VILLA_DSP_SDS_DSP_COEF_DFE0_SELECT, 0x2}, 41 {VILLA_LINE_SDS_COMMON_SRX0_RX_CPB, 0x2003}, 42 {VILLA_DSP_SDS_SERDES_SRX_FFE_DELAY_CTRL, 0xF047}, 43 {VILLA_MSEQ_ENABLE_MSB, 0x0000}, 44 {VILLA_MSEQ_SPARE21_LSB, 0x6}, 45 {VILLA_MSEQ_RESET_COUNT_LSB, 0x0}, 46 {VILLA_MSEQ_SPARE12_MSB, 0x0000}, 47 /* 48 * to invert the receiver path, uncomment the next line 49 * write (VILLA_MSEQ_SPARE12_MSB, 0x4000) 50 * 51 * SPARE2_LSB is used to configure the device while in sr mode to 52 * enable power savings and to use the optical module LOS signal. 53 * in power savings mode, the internal prbs checker can not be used. 54 * if the optical module LOS signal is used as an input to the micro 55 * code, then the micro code will wait until the optical module 56 * LOS = 0 before turning on the adaptive equalizer. 57 * Setting SPARE2_LSB bit 0 to 1 places the devie in power savings mode 58 * while setting bit 0 to 0 disables power savings mode. 59 * Setting SPARE2_LSB bit 2 to 0 configures the device to use the 60 * optical module LOS signal while setting bit 2 to 1 configures the 61 * device so that it will ignore the optical module LOS SPARE2_LSB = 0 62 */ 63 64 /* enable power savings, ignore optical module LOS */ 65 {VILLA_MSEQ_SPARE2_LSB, 0x5}, 66 67 {VILLA_MSEQ_SPARE7_LSB, 0x1e}, 68 {VILLA_MSEQ_BANKSELECT, 0x4}, 69 {VILLA_MSEQ_SPARE9_LSB, 0x2}, 70 {VILLA_MSEQ_SPARE3_LSB, 0x0F53}, 71 {VILLA_MSEQ_SPARE3_MSB, 0x2006}, 72 {VILLA_MSEQ_SPARE8_LSB, 0x3FF7}, 73 {VILLA_MSEQ_SPARE8_MSB, 0x0A46}, 74 {VILLA_MSEQ_COEF8_FFE0_LSB, 0xD500}, 75 {VILLA_MSEQ_COEF8_FFE1_LSB, 0x0200}, 76 {VILLA_MSEQ_COEF8_FFE2_LSB, 0xBA00}, 77 {VILLA_MSEQ_COEF8_FFE3_LSB, 0x0100}, 78 {VILLA_MSEQ_COEF8_FFE4_LSB, 0x0300}, 79 {VILLA_MSEQ_COEF8_FFE5_LSB, 0x0300}, 80 {VILLA_MSEQ_COEF8_DFE0_LSB, 0x0700}, 81 {VILLA_MSEQ_COEF8_DFE0N_LSB, 0x0E00}, 82 {VILLA_MSEQ_COEF8_DFE1_LSB, 0x0B00}, 83 {VILLA_DSP_SDS_DSP_COEF_LARGE_LEAK, 0x2}, 84 {VILLA_DSP_SDS_SERDES_SRX_DAC_ENABLEB_LSB, 0xD000}, 85 {VILLA_MSEQ_POWER_DOWN_LSB, 0xFFFF}, 86 {VILLA_MSEQ_POWER_DOWN_MSB, 0x0}, 87 {VILLA_MSEQ_CAL_RX_SLICER, 0x80}, 88 {VILLA_DSP_SDS_SERDES_SRX_DAC_BIAS_SELECT1_MSB, 0x3f}, 89 {VILLA_GLOBAL_MSEQCLKCTRL, 0x4}, 90 {VILLA_MSEQ_OPTIONS, 0x7}, 91 92 /* set up min value for ffe1 */ 93 {VILLA_MSEQ_COEF_INIT_SEL, 0x2}, 94 {VILLA_DSP_SDS_DSP_PRECODEDINITFFE21, 0x41}, 95 96 /* CS4315_sr_rx_pre_eq_set_4in */ 97 {VILLA_GLOBAL_MSEQCLKCTRL, 0x8004}, 98 {VILLA_MSEQ_OPTIONS, 0xf}, 99 {VILLA_MSEQ_BANKSELECT, 0x4}, 100 {VILLA_MSEQ_PC, 0x0}, 101 102 /* for lengths from 3.5 to 4.5inches */ 103 {VILLA_MSEQ_SERDES_PARAM_LSB, 0x0306}, 104 {VILLA_MSEQ_SPARE25_LSB, 0x0306}, 105 {VILLA_MSEQ_SPARE21_LSB, 0x2}, 106 {VILLA_MSEQ_SPARE23_LSB, 0x2}, 107 {VILLA_MSEQ_CAL_RX_DFE_EQ, 0x0}, 108 109 {VILLA_GLOBAL_MSEQCLKCTRL, 0x4}, 110 {VILLA_MSEQ_OPTIONS, 0x7}, 111 112 /* CS4315_rx_drive_4inch */ 113 /* for length 4inches */ 114 {VILLA_GLOBAL_VILLA2_COMPATIBLE, 0x0000}, 115 {VILLA_HOST_SDS_COMMON_STX0_TX_OUTPUT_CTRLA, 0x3023}, 116 {VILLA_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLB, 0xc01E}, 117 118 /* CS4315_tx_drive_4inch */ 119 /* for length 4inches */ 120 {VILLA_GLOBAL_VILLA2_COMPATIBLE, 0x0000}, 121 {VILLA_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLA, 0x3023}, 122 {VILLA_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLB, 0xc01E}, 123 }; 124 125 void cs4340_upload_firmware(struct phy_device *phydev) 126 { 127 char line_temp[0x50] = {0}; 128 char reg_addr[0x50] = {0}; 129 char reg_data[0x50] = {0}; 130 int i, line_cnt = 0, column_cnt = 0; 131 struct cortina_reg_config fw_temp; 132 char *addr = NULL; 133 134 #if defined(CONFIG_SYS_CORTINA_FW_IN_NOR) || \ 135 defined(CONFIG_SYS_CORTINA_FW_IN_REMOTE) 136 137 addr = (char *)CONFIG_CORTINA_FW_ADDR; 138 #elif defined(CONFIG_SYS_CORTINA_FW_IN_NAND) 139 int ret; 140 size_t fw_length = CONFIG_CORTINA_FW_LENGTH; 141 142 addr = malloc(CONFIG_CORTINA_FW_LENGTH); 143 ret = nand_read(get_nand_dev_by_index(0), 144 (loff_t)CONFIG_CORTINA_FW_ADDR, 145 &fw_length, (u_char *)addr); 146 if (ret == -EUCLEAN) { 147 printf("NAND read of Cortina firmware at 0x%x failed %d\n", 148 CONFIG_CORTINA_FW_ADDR, ret); 149 } 150 #elif defined(CONFIG_SYS_CORTINA_FW_IN_SPIFLASH) 151 int ret; 152 struct spi_flash *ucode_flash; 153 154 addr = malloc(CONFIG_CORTINA_FW_LENGTH); 155 ucode_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS, 156 CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE); 157 if (!ucode_flash) { 158 puts("SF: probe for Cortina ucode failed\n"); 159 } else { 160 ret = spi_flash_read(ucode_flash, CONFIG_CORTINA_FW_ADDR, 161 CONFIG_CORTINA_FW_LENGTH, addr); 162 if (ret) 163 puts("SF: read for Cortina ucode failed\n"); 164 spi_flash_free(ucode_flash); 165 } 166 #elif defined(CONFIG_SYS_CORTINA_FW_IN_MMC) 167 int dev = CONFIG_SYS_MMC_ENV_DEV; 168 u32 cnt = CONFIG_CORTINA_FW_LENGTH / 512; 169 u32 blk = CONFIG_CORTINA_FW_ADDR / 512; 170 struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV); 171 172 if (!mmc) { 173 puts("Failed to find MMC device for Cortina ucode\n"); 174 } else { 175 addr = malloc(CONFIG_CORTINA_FW_LENGTH); 176 printf("MMC read: dev # %u, block # %u, count %u ...\n", 177 dev, blk, cnt); 178 mmc_init(mmc); 179 (void)mmc->block_dev.block_read(&mmc->block_dev, blk, cnt, 180 addr); 181 } 182 #endif 183 184 while (*addr != 'Q') { 185 i = 0; 186 187 while (*addr != 0x0a) { 188 line_temp[i++] = *addr++; 189 if (0x50 < i) { 190 printf("Not found Cortina PHY ucode at 0x%p\n", 191 (char *)CONFIG_CORTINA_FW_ADDR); 192 return; 193 } 194 } 195 196 addr++; /* skip '\n' */ 197 line_cnt++; 198 column_cnt = i; 199 line_temp[column_cnt] = '\0'; 200 201 if (CONFIG_CORTINA_FW_LENGTH < line_cnt) 202 return; 203 204 for (i = 0; i < column_cnt; i++) { 205 if (isspace(line_temp[i++])) 206 break; 207 } 208 209 memcpy(reg_addr, line_temp, i); 210 memcpy(reg_data, &line_temp[i], column_cnt - i); 211 strim(reg_addr); 212 strim(reg_data); 213 fw_temp.reg_addr = (simple_strtoul(reg_addr, NULL, 0)) & 0xffff; 214 fw_temp.reg_value = (simple_strtoul(reg_data, NULL, 0)) & 215 0xffff; 216 phy_write(phydev, 0x00, fw_temp.reg_addr, fw_temp.reg_value); 217 } 218 } 219 #endif 220 221 int cs4340_phy_init(struct phy_device *phydev) 222 { 223 #ifndef CORTINA_NO_FW_UPLOAD 224 int timeout = 100; /* 100ms */ 225 #endif 226 int reg_value; 227 228 /* 229 * Cortina phy has provision to store 230 * phy firmware in attached dedicated EEPROM. 231 * Boards designed with EEPROM attached to Cortina 232 * does not require FW upload. 233 */ 234 #ifndef CORTINA_NO_FW_UPLOAD 235 /* step1: BIST test */ 236 phy_write(phydev, 0x00, VILLA_GLOBAL_MSEQCLKCTRL, 0x0004); 237 phy_write(phydev, 0x00, VILLA_GLOBAL_LINE_SOFT_RESET, 0x0000); 238 phy_write(phydev, 0x00, VILLA_GLOBAL_BIST_CONTROL, 0x0001); 239 while (--timeout) { 240 reg_value = phy_read(phydev, 0x00, VILLA_GLOBAL_BIST_STATUS); 241 if (reg_value & mseq_edc_bist_done) { 242 if (0 == (reg_value & mseq_edc_bist_fail)) 243 break; 244 } 245 udelay(1000); 246 } 247 248 if (!timeout) { 249 printf("%s BIST mseq_edc_bist_done timeout!\n", __func__); 250 return -1; 251 } 252 253 /* setp2: upload ucode */ 254 cs4340_upload_firmware(phydev); 255 #endif 256 reg_value = phy_read(phydev, 0x00, VILLA_GLOBAL_DWNLD_CHECKSUM_STATUS); 257 if (reg_value) { 258 debug("%s checksum status failed.\n", __func__); 259 return -1; 260 } 261 262 return 0; 263 } 264 265 int cs4340_config(struct phy_device *phydev) 266 { 267 cs4340_phy_init(phydev); 268 return 0; 269 } 270 271 int cs4340_probe(struct phy_device *phydev) 272 { 273 phydev->flags = PHY_FLAG_BROKEN_RESET; 274 return 0; 275 } 276 277 int cs4340_startup(struct phy_device *phydev) 278 { 279 phydev->link = 1; 280 281 /* For now just lie and say it's 10G all the time */ 282 phydev->speed = SPEED_10000; 283 phydev->duplex = DUPLEX_FULL; 284 return 0; 285 } 286 287 int cs4223_phy_init(struct phy_device *phydev) 288 { 289 int reg_value; 290 291 reg_value = phy_read(phydev, 0x00, CS4223_EEPROM_STATUS); 292 if (!(reg_value & CS4223_EEPROM_FIRMWARE_LOADDONE)) { 293 printf("%s CS4223 Firmware not present in EERPOM\n", __func__); 294 return -ENOSYS; 295 } 296 297 return 0; 298 } 299 300 int cs4223_config(struct phy_device *phydev) 301 { 302 return cs4223_phy_init(phydev); 303 } 304 305 int cs4223_probe(struct phy_device *phydev) 306 { 307 phydev->flags = PHY_FLAG_BROKEN_RESET; 308 return 0; 309 } 310 311 int cs4223_startup(struct phy_device *phydev) 312 { 313 phydev->link = 1; 314 phydev->speed = SPEED_10000; 315 phydev->duplex = DUPLEX_FULL; 316 return 0; 317 } 318 319 struct phy_driver cs4340_driver = { 320 .name = "Cortina CS4315/CS4340", 321 .uid = PHY_UID_CS4340, 322 .mask = 0xfffffff0, 323 .features = PHY_10G_FEATURES, 324 .mmds = (MDIO_DEVS_PMAPMD | MDIO_DEVS_PCS | 325 MDIO_DEVS_PHYXS | MDIO_DEVS_AN | 326 MDIO_DEVS_VEND1 | MDIO_DEVS_VEND2), 327 .config = &cs4340_config, 328 .probe = &cs4340_probe, 329 .startup = &cs4340_startup, 330 .shutdown = &gen10g_shutdown, 331 }; 332 333 struct phy_driver cs4223_driver = { 334 .name = "Cortina CS4223", 335 .uid = PHY_UID_CS4223, 336 .mask = 0x0ffff00f, 337 .features = PHY_10G_FEATURES, 338 .mmds = (MDIO_DEVS_PMAPMD | MDIO_DEVS_PCS | 339 MDIO_DEVS_AN), 340 .config = &cs4223_config, 341 .probe = &cs4223_probe, 342 .startup = &cs4223_startup, 343 .shutdown = &gen10g_shutdown, 344 }; 345 346 int phy_cortina_init(void) 347 { 348 phy_register(&cs4340_driver); 349 phy_register(&cs4223_driver); 350 return 0; 351 } 352 353 int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id) 354 { 355 int phy_reg; 356 357 /* Cortina PHY has non-standard offset of PHY ID registers */ 358 phy_reg = bus->read(bus, addr, 0, VILLA_GLOBAL_CHIP_ID_LSB); 359 if (phy_reg < 0) 360 return -EIO; 361 *phy_id = (phy_reg & 0xffff) << 16; 362 363 phy_reg = bus->read(bus, addr, 0, VILLA_GLOBAL_CHIP_ID_MSB); 364 if (phy_reg < 0) 365 return -EIO; 366 *phy_id |= (phy_reg & 0xffff); 367 368 if ((*phy_id == PHY_UID_CS4340) || (*phy_id == PHY_UID_CS4223)) 369 return 0; 370 371 /* 372 * If Cortina PHY not detected, 373 * try generic way to find PHY ID registers 374 */ 375 phy_reg = bus->read(bus, addr, devad, MII_PHYSID1); 376 if (phy_reg < 0) 377 return -EIO; 378 *phy_id = (phy_reg & 0xffff) << 16; 379 380 phy_reg = bus->read(bus, addr, devad, MII_PHYSID2); 381 if (phy_reg < 0) 382 return -EIO; 383 *phy_id |= (phy_reg & 0xffff); 384 385 return 0; 386 } 387
