1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * rtl8169.c : U-Boot driver for the RealTek RTL8169 4 * 5 * Masami Komiya (mkomiya (at) sonare.it) 6 * 7 * Most part is taken from r8169.c of etherboot 8 * 9 */ 10 11 /************************************************************************** 12 * r8169.c: Etherboot device driver for the RealTek RTL-8169 Gigabit 13 * Written 2003 by Timothy Legge <tlegge (at) rogers.com> 14 * 15 * Portions of this code based on: 16 * r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver 17 * for Linux kernel 2.4.x. 18 * 19 * Written 2002 ShuChen <shuchen (at) realtek.com.tw> 20 * See Linux Driver for full information 21 * 22 * Linux Driver Version 1.27a, 10.02.2002 23 * 24 * Thanks to: 25 * Jean Chen of RealTek Semiconductor Corp. for 26 * providing the evaluation NIC used to develop 27 * this driver. RealTek's support for Etherboot 28 * is appreciated. 29 * 30 * REVISION HISTORY: 31 * ================ 32 * 33 * v1.0 11-26-2003 timlegge Initial port of Linux driver 34 * v1.5 01-17-2004 timlegge Initial driver output cleanup 35 * 36 * Indent Options: indent -kr -i8 37 ***************************************************************************/ 38 /* 39 * 26 August 2006 Mihai Georgian <u-boot (at) linuxnotincluded.org.uk> 40 * Modified to use le32_to_cpu and cpu_to_le32 properly 41 */ 42 #include <common.h> 43 #include <dm.h> 44 #include <errno.h> 45 #include <malloc.h> 46 #include <memalign.h> 47 #include <net.h> 48 #ifndef CONFIG_DM_ETH 49 #include <netdev.h> 50 #endif 51 #include <asm/io.h> 52 #include <pci.h> 53 54 #undef DEBUG_RTL8169 55 #undef DEBUG_RTL8169_TX 56 #undef DEBUG_RTL8169_RX 57 58 #define drv_version "v1.5" 59 #define drv_date "01-17-2004" 60 61 static unsigned long ioaddr; 62 63 /* Condensed operations for readability. */ 64 #define currticks() get_timer(0) 65 66 /* media options */ 67 #define MAX_UNITS 8 68 static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 }; 69 70 /* MAC address length*/ 71 #define MAC_ADDR_LEN 6 72 73 /* max supported gigabit ethernet frame size -- must be at least (dev->mtu+14+4).*/ 74 #define MAX_ETH_FRAME_SIZE 1536 75 76 #define TX_FIFO_THRESH 256 /* In bytes */ 77 78 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */ 79 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ 80 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ 81 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */ 82 #define RxPacketMaxSize 0x0800 /* Maximum size supported is 16K-1 */ 83 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ 84 85 #define NUM_TX_DESC 1 /* Number of Tx descriptor registers */ 86 #ifdef CONFIG_SYS_RX_ETH_BUFFER 87 #define NUM_RX_DESC CONFIG_SYS_RX_ETH_BUFFER 88 #else 89 #define NUM_RX_DESC 4 /* Number of Rx descriptor registers */ 90 #endif 91 #define RX_BUF_SIZE 1536 /* Rx Buffer size */ 92 #define RX_BUF_LEN 8192 93 94 #define RTL_MIN_IO_SIZE 0x80 95 #define TX_TIMEOUT (6*HZ) 96 97 /* write/read MMIO register. Notice: {read,write}[wl] do the necessary swapping */ 98 #define RTL_W8(reg, val8) writeb((val8), ioaddr + (reg)) 99 #define RTL_W16(reg, val16) writew((val16), ioaddr + (reg)) 100 #define RTL_W32(reg, val32) writel((val32), ioaddr + (reg)) 101 #define RTL_R8(reg) readb(ioaddr + (reg)) 102 #define RTL_R16(reg) readw(ioaddr + (reg)) 103 #define RTL_R32(reg) readl(ioaddr + (reg)) 104 105 #define ETH_FRAME_LEN MAX_ETH_FRAME_SIZE 106 #define ETH_ALEN MAC_ADDR_LEN 107 #define ETH_ZLEN 60 108 109 #define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)(unsigned long)dev->priv, \ 110 (pci_addr_t)(unsigned long)a) 111 #define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)(unsigned long)dev->priv, \ 112 (phys_addr_t)a) 113 114 enum RTL8169_registers { 115 MAC0 = 0, /* Ethernet hardware address. */ 116 MAR0 = 8, /* Multicast filter. */ 117 TxDescStartAddrLow = 0x20, 118 TxDescStartAddrHigh = 0x24, 119 TxHDescStartAddrLow = 0x28, 120 TxHDescStartAddrHigh = 0x2c, 121 FLASH = 0x30, 122 ERSR = 0x36, 123 ChipCmd = 0x37, 124 TxPoll = 0x38, 125 IntrMask = 0x3C, 126 IntrStatus = 0x3E, 127 TxConfig = 0x40, 128 RxConfig = 0x44, 129 RxMissed = 0x4C, 130 Cfg9346 = 0x50, 131 Config0 = 0x51, 132 Config1 = 0x52, 133 Config2 = 0x53, 134 Config3 = 0x54, 135 Config4 = 0x55, 136 Config5 = 0x56, 137 MultiIntr = 0x5C, 138 PHYAR = 0x60, 139 TBICSR = 0x64, 140 TBI_ANAR = 0x68, 141 TBI_LPAR = 0x6A, 142 PHYstatus = 0x6C, 143 RxMaxSize = 0xDA, 144 CPlusCmd = 0xE0, 145 RxDescStartAddrLow = 0xE4, 146 RxDescStartAddrHigh = 0xE8, 147 EarlyTxThres = 0xEC, 148 FuncEvent = 0xF0, 149 FuncEventMask = 0xF4, 150 FuncPresetState = 0xF8, 151 FuncForceEvent = 0xFC, 152 }; 153 154 enum RTL8169_register_content { 155 /*InterruptStatusBits */ 156 SYSErr = 0x8000, 157 PCSTimeout = 0x4000, 158 SWInt = 0x0100, 159 TxDescUnavail = 0x80, 160 RxFIFOOver = 0x40, 161 RxUnderrun = 0x20, 162 RxOverflow = 0x10, 163 TxErr = 0x08, 164 TxOK = 0x04, 165 RxErr = 0x02, 166 RxOK = 0x01, 167 168 /*RxStatusDesc */ 169 RxRES = 0x00200000, 170 RxCRC = 0x00080000, 171 RxRUNT = 0x00100000, 172 RxRWT = 0x00400000, 173 174 /*ChipCmdBits */ 175 CmdReset = 0x10, 176 CmdRxEnb = 0x08, 177 CmdTxEnb = 0x04, 178 RxBufEmpty = 0x01, 179 180 /*Cfg9346Bits */ 181 Cfg9346_Lock = 0x00, 182 Cfg9346_Unlock = 0xC0, 183 184 /*rx_mode_bits */ 185 AcceptErr = 0x20, 186 AcceptRunt = 0x10, 187 AcceptBroadcast = 0x08, 188 AcceptMulticast = 0x04, 189 AcceptMyPhys = 0x02, 190 AcceptAllPhys = 0x01, 191 192 /*RxConfigBits */ 193 RxCfgFIFOShift = 13, 194 RxCfgDMAShift = 8, 195 196 /*TxConfigBits */ 197 TxInterFrameGapShift = 24, 198 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ 199 200 /*rtl8169_PHYstatus */ 201 TBI_Enable = 0x80, 202 TxFlowCtrl = 0x40, 203 RxFlowCtrl = 0x20, 204 _1000bpsF = 0x10, 205 _100bps = 0x08, 206 _10bps = 0x04, 207 LinkStatus = 0x02, 208 FullDup = 0x01, 209 210 /*GIGABIT_PHY_registers */ 211 PHY_CTRL_REG = 0, 212 PHY_STAT_REG = 1, 213 PHY_AUTO_NEGO_REG = 4, 214 PHY_1000_CTRL_REG = 9, 215 216 /*GIGABIT_PHY_REG_BIT */ 217 PHY_Restart_Auto_Nego = 0x0200, 218 PHY_Enable_Auto_Nego = 0x1000, 219 220 /* PHY_STAT_REG = 1; */ 221 PHY_Auto_Nego_Comp = 0x0020, 222 223 /* PHY_AUTO_NEGO_REG = 4; */ 224 PHY_Cap_10_Half = 0x0020, 225 PHY_Cap_10_Full = 0x0040, 226 PHY_Cap_100_Half = 0x0080, 227 PHY_Cap_100_Full = 0x0100, 228 229 /* PHY_1000_CTRL_REG = 9; */ 230 PHY_Cap_1000_Full = 0x0200, 231 232 PHY_Cap_Null = 0x0, 233 234 /*_MediaType*/ 235 _10_Half = 0x01, 236 _10_Full = 0x02, 237 _100_Half = 0x04, 238 _100_Full = 0x08, 239 _1000_Full = 0x10, 240 241 /*_TBICSRBit*/ 242 TBILinkOK = 0x02000000, 243 }; 244 245 static struct { 246 const char *name; 247 u8 version; /* depend on RTL8169 docs */ 248 u32 RxConfigMask; /* should clear the bits supported by this chip */ 249 } rtl_chip_info[] = { 250 {"RTL-8169", 0x00, 0xff7e1880,}, 251 {"RTL-8169", 0x04, 0xff7e1880,}, 252 {"RTL-8169", 0x00, 0xff7e1880,}, 253 {"RTL-8169s/8110s", 0x02, 0xff7e1880,}, 254 {"RTL-8169s/8110s", 0x04, 0xff7e1880,}, 255 {"RTL-8169sb/8110sb", 0x10, 0xff7e1880,}, 256 {"RTL-8169sc/8110sc", 0x18, 0xff7e1880,}, 257 {"RTL-8168b/8111sb", 0x30, 0xff7e1880,}, 258 {"RTL-8168b/8111sb", 0x38, 0xff7e1880,}, 259 {"RTL-8168d/8111d", 0x28, 0xff7e1880,}, 260 {"RTL-8168evl/8111evl", 0x2e, 0xff7e1880,}, 261 {"RTL-8168/8111g", 0x4c, 0xff7e1880,}, 262 {"RTL-8101e", 0x34, 0xff7e1880,}, 263 {"RTL-8100e", 0x32, 0xff7e1880,}, 264 }; 265 266 enum _DescStatusBit { 267 OWNbit = 0x80000000, 268 EORbit = 0x40000000, 269 FSbit = 0x20000000, 270 LSbit = 0x10000000, 271 }; 272 273 struct TxDesc { 274 u32 status; 275 u32 vlan_tag; 276 u32 buf_addr; 277 u32 buf_Haddr; 278 }; 279 280 struct RxDesc { 281 u32 status; 282 u32 vlan_tag; 283 u32 buf_addr; 284 u32 buf_Haddr; 285 }; 286 287 static unsigned char rxdata[RX_BUF_LEN]; 288 289 #define RTL8169_DESC_SIZE 16 290 291 #if ARCH_DMA_MINALIGN > 256 292 # define RTL8169_ALIGN ARCH_DMA_MINALIGN 293 #else 294 # define RTL8169_ALIGN 256 295 #endif 296 297 /* 298 * Warn if the cache-line size is larger than the descriptor size. In such 299 * cases the driver will likely fail because the CPU needs to flush the cache 300 * when requeuing RX buffers, therefore descriptors written by the hardware 301 * may be discarded. 302 * 303 * This can be fixed by defining CONFIG_SYS_NONCACHED_MEMORY which will cause 304 * the driver to allocate descriptors from a pool of non-cached memory. 305 */ 306 #if RTL8169_DESC_SIZE < ARCH_DMA_MINALIGN 307 #if !defined(CONFIG_SYS_NONCACHED_MEMORY) && \ 308 !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_X86) 309 #warning cache-line size is larger than descriptor size 310 #endif 311 #endif 312 313 /* 314 * Create a static buffer of size RX_BUF_SZ for each TX Descriptor. All 315 * descriptors point to a part of this buffer. 316 */ 317 DEFINE_ALIGN_BUFFER(u8, txb, NUM_TX_DESC * RX_BUF_SIZE, RTL8169_ALIGN); 318 319 /* 320 * Create a static buffer of size RX_BUF_SZ for each RX Descriptor. All 321 * descriptors point to a part of this buffer. 322 */ 323 DEFINE_ALIGN_BUFFER(u8, rxb, NUM_RX_DESC * RX_BUF_SIZE, RTL8169_ALIGN); 324 325 struct rtl8169_private { 326 ulong iobase; 327 void *mmio_addr; /* memory map physical address */ 328 int chipset; 329 unsigned long cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ 330 unsigned long cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ 331 unsigned long dirty_tx; 332 struct TxDesc *TxDescArray; /* Index of 256-alignment Tx Descriptor buffer */ 333 struct RxDesc *RxDescArray; /* Index of 256-alignment Rx Descriptor buffer */ 334 unsigned char *RxBufferRings; /* Index of Rx Buffer */ 335 unsigned char *RxBufferRing[NUM_RX_DESC]; /* Index of Rx Buffer array */ 336 unsigned char *Tx_skbuff[NUM_TX_DESC]; 337 } tpx; 338 339 static struct rtl8169_private *tpc; 340 341 static const unsigned int rtl8169_rx_config = 342 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift); 343 344 static struct pci_device_id supported[] = { 345 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167) }, 346 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168) }, 347 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169) }, 348 {} 349 }; 350 351 void mdio_write(int RegAddr, int value) 352 { 353 int i; 354 355 RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value); 356 udelay(1000); 357 358 for (i = 2000; i > 0; i--) { 359 /* Check if the RTL8169 has completed writing to the specified MII register */ 360 if (!(RTL_R32(PHYAR) & 0x80000000)) { 361 break; 362 } else { 363 udelay(100); 364 } 365 } 366 } 367 368 int mdio_read(int RegAddr) 369 { 370 int i, value = -1; 371 372 RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16); 373 udelay(1000); 374 375 for (i = 2000; i > 0; i--) { 376 /* Check if the RTL8169 has completed retrieving data from the specified MII register */ 377 if (RTL_R32(PHYAR) & 0x80000000) { 378 value = (int) (RTL_R32(PHYAR) & 0xFFFF); 379 break; 380 } else { 381 udelay(100); 382 } 383 } 384 return value; 385 } 386 387 static int rtl8169_init_board(unsigned long dev_iobase, const char *name) 388 { 389 int i; 390 u32 tmp; 391 392 #ifdef DEBUG_RTL8169 393 printf ("%s\n", __FUNCTION__); 394 #endif 395 ioaddr = dev_iobase; 396 397 /* Soft reset the chip. */ 398 RTL_W8(ChipCmd, CmdReset); 399 400 /* Check that the chip has finished the reset. */ 401 for (i = 1000; i > 0; i--) 402 if ((RTL_R8(ChipCmd) & CmdReset) == 0) 403 break; 404 else 405 udelay(10); 406 407 /* identify chip attached to board */ 408 tmp = RTL_R32(TxConfig); 409 tmp = ((tmp & 0x7c000000) + ((tmp & 0x00800000) << 2)) >> 24; 410 411 for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--){ 412 if (tmp == rtl_chip_info[i].version) { 413 tpc->chipset = i; 414 goto match; 415 } 416 } 417 418 /* if unknown chip, assume array element #0, original RTL-8169 in this case */ 419 printf("PCI device %s: unknown chip version, assuming RTL-8169\n", 420 name); 421 printf("PCI device: TxConfig = 0x%lX\n", (unsigned long) RTL_R32(TxConfig)); 422 tpc->chipset = 0; 423 424 match: 425 return 0; 426 } 427 428 /* 429 * TX and RX descriptors are 16 bytes. This causes problems with the cache 430 * maintenance on CPUs where the cache-line size exceeds the size of these 431 * descriptors. What will happen is that when the driver receives a packet 432 * it will be immediately requeued for the hardware to reuse. The CPU will 433 * therefore need to flush the cache-line containing the descriptor, which 434 * will cause all other descriptors in the same cache-line to be flushed 435 * along with it. If one of those descriptors had been written to by the 436 * device those changes (and the associated packet) will be lost. 437 * 438 * To work around this, we make use of non-cached memory if available. If 439 * descriptors are mapped uncached there's no need to manually flush them 440 * or invalidate them. 441 * 442 * Note that this only applies to descriptors. The packet data buffers do 443 * not have the same constraints since they are 1536 bytes large, so they 444 * are unlikely to share cache-lines. 445 */ 446 static void *rtl_alloc_descs(unsigned int num) 447 { 448 size_t size = num * RTL8169_DESC_SIZE; 449 450 #ifdef CONFIG_SYS_NONCACHED_MEMORY 451 return (void *)noncached_alloc(size, RTL8169_ALIGN); 452 #else 453 return memalign(RTL8169_ALIGN, size); 454 #endif 455 } 456 457 /* 458 * Cache maintenance functions. These are simple wrappers around the more 459 * general purpose flush_cache() and invalidate_dcache_range() functions. 460 */ 461 462 static void rtl_inval_rx_desc(struct RxDesc *desc) 463 { 464 #ifndef CONFIG_SYS_NONCACHED_MEMORY 465 unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1); 466 unsigned long end = ALIGN(start + sizeof(*desc), ARCH_DMA_MINALIGN); 467 468 invalidate_dcache_range(start, end); 469 #endif 470 } 471 472 static void rtl_flush_rx_desc(struct RxDesc *desc) 473 { 474 #ifndef CONFIG_SYS_NONCACHED_MEMORY 475 flush_cache((unsigned long)desc, sizeof(*desc)); 476 #endif 477 } 478 479 static void rtl_inval_tx_desc(struct TxDesc *desc) 480 { 481 #ifndef CONFIG_SYS_NONCACHED_MEMORY 482 unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1); 483 unsigned long end = ALIGN(start + sizeof(*desc), ARCH_DMA_MINALIGN); 484 485 invalidate_dcache_range(start, end); 486 #endif 487 } 488 489 static void rtl_flush_tx_desc(struct TxDesc *desc) 490 { 491 #ifndef CONFIG_SYS_NONCACHED_MEMORY 492 flush_cache((unsigned long)desc, sizeof(*desc)); 493 #endif 494 } 495 496 static void rtl_inval_buffer(void *buf, size_t size) 497 { 498 unsigned long start = (unsigned long)buf & ~(ARCH_DMA_MINALIGN - 1); 499 unsigned long end = ALIGN(start + size, ARCH_DMA_MINALIGN); 500 501 invalidate_dcache_range(start, end); 502 } 503 504 static void rtl_flush_buffer(void *buf, size_t size) 505 { 506 flush_cache((unsigned long)buf, size); 507 } 508 509 /************************************************************************** 510 RECV - Receive a frame 511 ***************************************************************************/ 512 #ifdef CONFIG_DM_ETH 513 static int rtl_recv_common(struct udevice *dev, unsigned long dev_iobase, 514 uchar **packetp) 515 #else 516 static int rtl_recv_common(pci_dev_t dev, unsigned long dev_iobase, 517 uchar **packetp) 518 #endif 519 { 520 /* return true if there's an ethernet packet ready to read */ 521 /* nic->packet should contain data on return */ 522 /* nic->packetlen should contain length of data */ 523 int cur_rx; 524 int length = 0; 525 526 #ifdef DEBUG_RTL8169_RX 527 printf ("%s\n", __FUNCTION__); 528 #endif 529 ioaddr = dev_iobase; 530 531 cur_rx = tpc->cur_rx; 532 533 rtl_inval_rx_desc(&tpc->RxDescArray[cur_rx]); 534 535 if ((le32_to_cpu(tpc->RxDescArray[cur_rx].status) & OWNbit) == 0) { 536 if (!(le32_to_cpu(tpc->RxDescArray[cur_rx].status) & RxRES)) { 537 length = (int) (le32_to_cpu(tpc->RxDescArray[cur_rx]. 538 status) & 0x00001FFF) - 4; 539 540 rtl_inval_buffer(tpc->RxBufferRing[cur_rx], length); 541 memcpy(rxdata, tpc->RxBufferRing[cur_rx], length); 542 543 if (cur_rx == NUM_RX_DESC - 1) 544 tpc->RxDescArray[cur_rx].status = 545 cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE); 546 else 547 tpc->RxDescArray[cur_rx].status = 548 cpu_to_le32(OWNbit + RX_BUF_SIZE); 549 #ifdef CONFIG_DM_ETH 550 tpc->RxDescArray[cur_rx].buf_addr = cpu_to_le32( 551 dm_pci_mem_to_phys(dev, 552 (pci_addr_t)(unsigned long) 553 tpc->RxBufferRing[cur_rx])); 554 #else 555 tpc->RxDescArray[cur_rx].buf_addr = cpu_to_le32( 556 pci_mem_to_phys(dev, (pci_addr_t)(unsigned long) 557 tpc->RxBufferRing[cur_rx])); 558 #endif 559 rtl_flush_rx_desc(&tpc->RxDescArray[cur_rx]); 560 #ifdef CONFIG_DM_ETH 561 *packetp = rxdata; 562 #else 563 net_process_received_packet(rxdata, length); 564 #endif 565 } else { 566 puts("Error Rx"); 567 length = -EIO; 568 } 569 cur_rx = (cur_rx + 1) % NUM_RX_DESC; 570 tpc->cur_rx = cur_rx; 571 return length; 572 573 } else { 574 ushort sts = RTL_R8(IntrStatus); 575 RTL_W8(IntrStatus, sts & ~(TxErr | RxErr | SYSErr)); 576 udelay(100); /* wait */ 577 } 578 tpc->cur_rx = cur_rx; 579 return (0); /* initially as this is called to flush the input */ 580 } 581 582 #ifdef CONFIG_DM_ETH 583 int rtl8169_eth_recv(struct udevice *dev, int flags, uchar **packetp) 584 { 585 struct rtl8169_private *priv = dev_get_priv(dev); 586 587 return rtl_recv_common(dev, priv->iobase, packetp); 588 } 589 #else 590 static int rtl_recv(struct eth_device *dev) 591 { 592 return rtl_recv_common((pci_dev_t)(unsigned long)dev->priv, 593 dev->iobase, NULL); 594 } 595 #endif /* nCONFIG_DM_ETH */ 596 597 #define HZ 1000 598 /************************************************************************** 599 SEND - Transmit a frame 600 ***************************************************************************/ 601 #ifdef CONFIG_DM_ETH 602 static int rtl_send_common(struct udevice *dev, unsigned long dev_iobase, 603 void *packet, int length) 604 #else 605 static int rtl_send_common(pci_dev_t dev, unsigned long dev_iobase, 606 void *packet, int length) 607 #endif 608 { 609 /* send the packet to destination */ 610 611 u32 to; 612 u8 *ptxb; 613 int entry = tpc->cur_tx % NUM_TX_DESC; 614 u32 len = length; 615 int ret; 616 617 #ifdef DEBUG_RTL8169_TX 618 int stime = currticks(); 619 printf ("%s\n", __FUNCTION__); 620 printf("sending %d bytes\n", len); 621 #endif 622 623 ioaddr = dev_iobase; 624 625 /* point to the current txb incase multiple tx_rings are used */ 626 ptxb = tpc->Tx_skbuff[entry * MAX_ETH_FRAME_SIZE]; 627 memcpy(ptxb, (char *)packet, (int)length); 628 629 while (len < ETH_ZLEN) 630 ptxb[len++] = '\0'; 631 632 rtl_flush_buffer(ptxb, ALIGN(len, RTL8169_ALIGN)); 633 634 tpc->TxDescArray[entry].buf_Haddr = 0; 635 #ifdef CONFIG_DM_ETH 636 tpc->TxDescArray[entry].buf_addr = cpu_to_le32( 637 dm_pci_mem_to_phys(dev, (pci_addr_t)(unsigned long)ptxb)); 638 #else 639 tpc->TxDescArray[entry].buf_addr = cpu_to_le32( 640 pci_mem_to_phys(dev, (pci_addr_t)(unsigned long)ptxb)); 641 #endif 642 if (entry != (NUM_TX_DESC - 1)) { 643 tpc->TxDescArray[entry].status = 644 cpu_to_le32((OWNbit | FSbit | LSbit) | 645 ((len > ETH_ZLEN) ? len : ETH_ZLEN)); 646 } else { 647 tpc->TxDescArray[entry].status = 648 cpu_to_le32((OWNbit | EORbit | FSbit | LSbit) | 649 ((len > ETH_ZLEN) ? len : ETH_ZLEN)); 650 } 651 rtl_flush_tx_desc(&tpc->TxDescArray[entry]); 652 RTL_W8(TxPoll, 0x40); /* set polling bit */ 653 654 tpc->cur_tx++; 655 to = currticks() + TX_TIMEOUT; 656 do { 657 rtl_inval_tx_desc(&tpc->TxDescArray[entry]); 658 } while ((le32_to_cpu(tpc->TxDescArray[entry].status) & OWNbit) 659 && (currticks() < to)); /* wait */ 660 661 if (currticks() >= to) { 662 #ifdef DEBUG_RTL8169_TX 663 puts("tx timeout/error\n"); 664 printf("%s elapsed time : %lu\n", __func__, currticks()-stime); 665 #endif 666 ret = -ETIMEDOUT; 667 } else { 668 #ifdef DEBUG_RTL8169_TX 669 puts("tx done\n"); 670 #endif 671 ret = 0; 672 } 673 /* Delay to make net console (nc) work properly */ 674 udelay(20); 675 return ret; 676 } 677 678 #ifdef CONFIG_DM_ETH 679 int rtl8169_eth_send(struct udevice *dev, void *packet, int length) 680 { 681 struct rtl8169_private *priv = dev_get_priv(dev); 682 683 return rtl_send_common(dev, priv->iobase, packet, length); 684 } 685 686 #else 687 static int rtl_send(struct eth_device *dev, void *packet, int length) 688 { 689 return rtl_send_common((pci_dev_t)(unsigned long)dev->priv, 690 dev->iobase, packet, length); 691 } 692 #endif 693 694 static void rtl8169_set_rx_mode(void) 695 { 696 u32 mc_filter[2]; /* Multicast hash filter */ 697 int rx_mode; 698 u32 tmp = 0; 699 700 #ifdef DEBUG_RTL8169 701 printf ("%s\n", __FUNCTION__); 702 #endif 703 704 /* IFF_ALLMULTI */ 705 /* Too many to filter perfectly -- accept all multicasts. */ 706 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; 707 mc_filter[1] = mc_filter[0] = 0xffffffff; 708 709 tmp = rtl8169_rx_config | rx_mode | (RTL_R32(RxConfig) & 710 rtl_chip_info[tpc->chipset].RxConfigMask); 711 712 RTL_W32(RxConfig, tmp); 713 RTL_W32(MAR0 + 0, mc_filter[0]); 714 RTL_W32(MAR0 + 4, mc_filter[1]); 715 } 716 717 #ifdef CONFIG_DM_ETH 718 static void rtl8169_hw_start(struct udevice *dev) 719 #else 720 static void rtl8169_hw_start(pci_dev_t dev) 721 #endif 722 { 723 u32 i; 724 725 #ifdef DEBUG_RTL8169 726 int stime = currticks(); 727 printf ("%s\n", __FUNCTION__); 728 #endif 729 730 #if 0 731 /* Soft reset the chip. */ 732 RTL_W8(ChipCmd, CmdReset); 733 734 /* Check that the chip has finished the reset. */ 735 for (i = 1000; i > 0; i--) { 736 if ((RTL_R8(ChipCmd) & CmdReset) == 0) 737 break; 738 else 739 udelay(10); 740 } 741 #endif 742 743 RTL_W8(Cfg9346, Cfg9346_Unlock); 744 745 /* RTL-8169sb/8110sb or previous version */ 746 if (tpc->chipset <= 5) 747 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); 748 749 RTL_W8(EarlyTxThres, EarlyTxThld); 750 751 /* For gigabit rtl8169 */ 752 RTL_W16(RxMaxSize, RxPacketMaxSize); 753 754 /* Set Rx Config register */ 755 i = rtl8169_rx_config | (RTL_R32(RxConfig) & 756 rtl_chip_info[tpc->chipset].RxConfigMask); 757 RTL_W32(RxConfig, i); 758 759 /* Set DMA burst size and Interframe Gap Time */ 760 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | 761 (InterFrameGap << TxInterFrameGapShift)); 762 763 764 tpc->cur_rx = 0; 765 766 #ifdef CONFIG_DM_ETH 767 RTL_W32(TxDescStartAddrLow, dm_pci_mem_to_phys(dev, 768 (pci_addr_t)(unsigned long)tpc->TxDescArray)); 769 #else 770 RTL_W32(TxDescStartAddrLow, pci_mem_to_phys(dev, 771 (pci_addr_t)(unsigned long)tpc->TxDescArray)); 772 #endif 773 RTL_W32(TxDescStartAddrHigh, (unsigned long)0); 774 #ifdef CONFIG_DM_ETH 775 RTL_W32(RxDescStartAddrLow, dm_pci_mem_to_phys( 776 dev, (pci_addr_t)(unsigned long)tpc->RxDescArray)); 777 #else 778 RTL_W32(RxDescStartAddrLow, pci_mem_to_phys( 779 dev, (pci_addr_t)(unsigned long)tpc->RxDescArray)); 780 #endif 781 RTL_W32(RxDescStartAddrHigh, (unsigned long)0); 782 783 /* RTL-8169sc/8110sc or later version */ 784 if (tpc->chipset > 5) 785 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); 786 787 RTL_W8(Cfg9346, Cfg9346_Lock); 788 udelay(10); 789 790 RTL_W32(RxMissed, 0); 791 792 rtl8169_set_rx_mode(); 793 794 /* no early-rx interrupts */ 795 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); 796 797 #ifdef DEBUG_RTL8169 798 printf("%s elapsed time : %lu\n", __func__, currticks()-stime); 799 #endif 800 } 801 802 #ifdef CONFIG_DM_ETH 803 static void rtl8169_init_ring(struct udevice *dev) 804 #else 805 static void rtl8169_init_ring(pci_dev_t dev) 806 #endif 807 { 808 int i; 809 810 #ifdef DEBUG_RTL8169 811 int stime = currticks(); 812 printf ("%s\n", __FUNCTION__); 813 #endif 814 815 tpc->cur_rx = 0; 816 tpc->cur_tx = 0; 817 tpc->dirty_tx = 0; 818 memset(tpc->TxDescArray, 0x0, NUM_TX_DESC * sizeof(struct TxDesc)); 819 memset(tpc->RxDescArray, 0x0, NUM_RX_DESC * sizeof(struct RxDesc)); 820 821 for (i = 0; i < NUM_TX_DESC; i++) { 822 tpc->Tx_skbuff[i] = &txb[i]; 823 } 824 825 for (i = 0; i < NUM_RX_DESC; i++) { 826 if (i == (NUM_RX_DESC - 1)) 827 tpc->RxDescArray[i].status = 828 cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE); 829 else 830 tpc->RxDescArray[i].status = 831 cpu_to_le32(OWNbit + RX_BUF_SIZE); 832 833 tpc->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE]; 834 #ifdef CONFIG_DM_ETH 835 tpc->RxDescArray[i].buf_addr = cpu_to_le32(dm_pci_mem_to_phys( 836 dev, (pci_addr_t)(unsigned long)tpc->RxBufferRing[i])); 837 #else 838 tpc->RxDescArray[i].buf_addr = cpu_to_le32(pci_mem_to_phys( 839 dev, (pci_addr_t)(unsigned long)tpc->RxBufferRing[i])); 840 #endif 841 rtl_flush_rx_desc(&tpc->RxDescArray[i]); 842 } 843 844 #ifdef DEBUG_RTL8169 845 printf("%s elapsed time : %lu\n", __func__, currticks()-stime); 846 #endif 847 } 848 849 #ifdef CONFIG_DM_ETH 850 static void rtl8169_common_start(struct udevice *dev, unsigned char *enetaddr, 851 unsigned long dev_iobase) 852 #else 853 static void rtl8169_common_start(pci_dev_t dev, unsigned char *enetaddr, 854 unsigned long dev_iobase) 855 #endif 856 { 857 int i; 858 859 #ifdef DEBUG_RTL8169 860 int stime = currticks(); 861 printf ("%s\n", __FUNCTION__); 862 #endif 863 864 ioaddr = dev_iobase; 865 866 rtl8169_init_ring(dev); 867 rtl8169_hw_start(dev); 868 /* Construct a perfect filter frame with the mac address as first match 869 * and broadcast for all others */ 870 for (i = 0; i < 192; i++) 871 txb[i] = 0xFF; 872 873 txb[0] = enetaddr[0]; 874 txb[1] = enetaddr[1]; 875 txb[2] = enetaddr[2]; 876 txb[3] = enetaddr[3]; 877 txb[4] = enetaddr[4]; 878 txb[5] = enetaddr[5]; 879 880 #ifdef DEBUG_RTL8169 881 printf("%s elapsed time : %lu\n", __func__, currticks()-stime); 882 #endif 883 } 884 885 #ifdef CONFIG_DM_ETH 886 static int rtl8169_eth_start(struct udevice *dev) 887 { 888 struct eth_pdata *plat = dev_get_platdata(dev); 889 struct rtl8169_private *priv = dev_get_priv(dev); 890 891 rtl8169_common_start(dev, plat->enetaddr, priv->iobase); 892 893 return 0; 894 } 895 #else 896 /************************************************************************** 897 RESET - Finish setting up the ethernet interface 898 ***************************************************************************/ 899 static int rtl_reset(struct eth_device *dev, bd_t *bis) 900 { 901 rtl8169_common_start((pci_dev_t)(unsigned long)dev->priv, 902 dev->enetaddr, dev->iobase); 903 904 return 0; 905 } 906 #endif /* nCONFIG_DM_ETH */ 907 908 static void rtl_halt_common(unsigned long dev_iobase) 909 { 910 int i; 911 912 #ifdef DEBUG_RTL8169 913 printf ("%s\n", __FUNCTION__); 914 #endif 915 916 ioaddr = dev_iobase; 917 918 /* Stop the chip's Tx and Rx DMA processes. */ 919 RTL_W8(ChipCmd, 0x00); 920 921 /* Disable interrupts by clearing the interrupt mask. */ 922 RTL_W16(IntrMask, 0x0000); 923 924 RTL_W32(RxMissed, 0); 925 926 for (i = 0; i < NUM_RX_DESC; i++) { 927 tpc->RxBufferRing[i] = NULL; 928 } 929 } 930 931 #ifdef CONFIG_DM_ETH 932 void rtl8169_eth_stop(struct udevice *dev) 933 { 934 struct rtl8169_private *priv = dev_get_priv(dev); 935 936 rtl_halt_common(priv->iobase); 937 } 938 #else 939 /************************************************************************** 940 HALT - Turn off ethernet interface 941 ***************************************************************************/ 942 static void rtl_halt(struct eth_device *dev) 943 { 944 rtl_halt_common(dev->iobase); 945 } 946 #endif 947 948 /************************************************************************** 949 INIT - Look for an adapter, this routine's visible to the outside 950 ***************************************************************************/ 951 952 #define board_found 1 953 #define valid_link 0 954 static int rtl_init(unsigned long dev_ioaddr, const char *name, 955 unsigned char *enetaddr) 956 { 957 static int board_idx = -1; 958 int i, rc; 959 int option = -1, Cap10_100 = 0, Cap1000 = 0; 960 961 #ifdef DEBUG_RTL8169 962 printf ("%s\n", __FUNCTION__); 963 #endif 964 ioaddr = dev_ioaddr; 965 966 board_idx++; 967 968 /* point to private storage */ 969 tpc = &tpx; 970 971 rc = rtl8169_init_board(ioaddr, name); 972 if (rc) 973 return rc; 974 975 /* Get MAC address. FIXME: read EEPROM */ 976 for (i = 0; i < MAC_ADDR_LEN; i++) 977 enetaddr[i] = RTL_R8(MAC0 + i); 978 979 #ifdef DEBUG_RTL8169 980 printf("chipset = %d\n", tpc->chipset); 981 printf("MAC Address"); 982 for (i = 0; i < MAC_ADDR_LEN; i++) 983 printf(":%02x", enetaddr[i]); 984 putc('\n'); 985 #endif 986 987 #ifdef DEBUG_RTL8169 988 /* Print out some hardware info */ 989 printf("%s: at ioaddr 0x%lx\n", name, ioaddr); 990 #endif 991 992 /* if TBI is not endbled */ 993 if (!(RTL_R8(PHYstatus) & TBI_Enable)) { 994 int val = mdio_read(PHY_AUTO_NEGO_REG); 995 996 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx]; 997 /* Force RTL8169 in 10/100/1000 Full/Half mode. */ 998 if (option > 0) { 999 #ifdef DEBUG_RTL8169 1000 printf("%s: Force-mode Enabled.\n", name); 1001 #endif 1002 Cap10_100 = 0, Cap1000 = 0; 1003 switch (option) { 1004 case _10_Half: 1005 Cap10_100 = PHY_Cap_10_Half; 1006 Cap1000 = PHY_Cap_Null; 1007 break; 1008 case _10_Full: 1009 Cap10_100 = PHY_Cap_10_Full; 1010 Cap1000 = PHY_Cap_Null; 1011 break; 1012 case _100_Half: 1013 Cap10_100 = PHY_Cap_100_Half; 1014 Cap1000 = PHY_Cap_Null; 1015 break; 1016 case _100_Full: 1017 Cap10_100 = PHY_Cap_100_Full; 1018 Cap1000 = PHY_Cap_Null; 1019 break; 1020 case _1000_Full: 1021 Cap10_100 = PHY_Cap_Null; 1022 Cap1000 = PHY_Cap_1000_Full; 1023 break; 1024 default: 1025 break; 1026 } 1027 mdio_write(PHY_AUTO_NEGO_REG, Cap10_100 | (val & 0x1F)); /* leave PHY_AUTO_NEGO_REG bit4:0 unchanged */ 1028 mdio_write(PHY_1000_CTRL_REG, Cap1000); 1029 } else { 1030 #ifdef DEBUG_RTL8169 1031 printf("%s: Auto-negotiation Enabled.\n", 1032 name); 1033 #endif 1034 /* enable 10/100 Full/Half Mode, leave PHY_AUTO_NEGO_REG bit4:0 unchanged */ 1035 mdio_write(PHY_AUTO_NEGO_REG, 1036 PHY_Cap_10_Half | PHY_Cap_10_Full | 1037 PHY_Cap_100_Half | PHY_Cap_100_Full | 1038 (val & 0x1F)); 1039 1040 /* enable 1000 Full Mode */ 1041 mdio_write(PHY_1000_CTRL_REG, PHY_Cap_1000_Full); 1042 1043 } 1044 1045 /* Enable auto-negotiation and restart auto-nigotiation */ 1046 mdio_write(PHY_CTRL_REG, 1047 PHY_Enable_Auto_Nego | PHY_Restart_Auto_Nego); 1048 udelay(100); 1049 1050 /* wait for auto-negotiation process */ 1051 for (i = 10000; i > 0; i--) { 1052 /* check if auto-negotiation complete */ 1053 if (mdio_read(PHY_STAT_REG) & PHY_Auto_Nego_Comp) { 1054 udelay(100); 1055 option = RTL_R8(PHYstatus); 1056 if (option & _1000bpsF) { 1057 #ifdef DEBUG_RTL8169 1058 printf("%s: 1000Mbps Full-duplex operation.\n", 1059 name); 1060 #endif 1061 } else { 1062 #ifdef DEBUG_RTL8169 1063 printf("%s: %sMbps %s-duplex operation.\n", 1064 name, 1065 (option & _100bps) ? "100" : 1066 "10", 1067 (option & FullDup) ? "Full" : 1068 "Half"); 1069 #endif 1070 } 1071 break; 1072 } else { 1073 udelay(100); 1074 } 1075 } /* end for-loop to wait for auto-negotiation process */ 1076 1077 } else { 1078 udelay(100); 1079 #ifdef DEBUG_RTL8169 1080 printf 1081 ("%s: 1000Mbps Full-duplex operation, TBI Link %s!\n", 1082 name, 1083 (RTL_R32(TBICSR) & TBILinkOK) ? "OK" : "Failed"); 1084 #endif 1085 } 1086 1087 1088 tpc->RxDescArray = rtl_alloc_descs(NUM_RX_DESC); 1089 if (!tpc->RxDescArray) 1090 return -ENOMEM; 1091 1092 tpc->TxDescArray = rtl_alloc_descs(NUM_TX_DESC); 1093 if (!tpc->TxDescArray) 1094 return -ENOMEM; 1095 1096 return 0; 1097 } 1098 1099 #ifndef CONFIG_DM_ETH 1100 int rtl8169_initialize(bd_t *bis) 1101 { 1102 pci_dev_t devno; 1103 int card_number = 0; 1104 struct eth_device *dev; 1105 u32 iobase; 1106 int idx=0; 1107 1108 while(1){ 1109 unsigned int region; 1110 u16 device; 1111 int err; 1112 1113 /* Find RTL8169 */ 1114 if ((devno = pci_find_devices(supported, idx++)) < 0) 1115 break; 1116 1117 pci_read_config_word(devno, PCI_DEVICE_ID, &device); 1118 switch (device) { 1119 case 0x8168: 1120 region = 2; 1121 break; 1122 1123 default: 1124 region = 1; 1125 break; 1126 } 1127 1128 pci_read_config_dword(devno, PCI_BASE_ADDRESS_0 + (region * 4), &iobase); 1129 iobase &= ~0xf; 1130 1131 debug ("rtl8169: REALTEK RTL8169 @0x%x\n", iobase); 1132 1133 dev = (struct eth_device *)malloc(sizeof *dev); 1134 if (!dev) { 1135 printf("Can not allocate memory of rtl8169\n"); 1136 break; 1137 } 1138 1139 memset(dev, 0, sizeof(*dev)); 1140 sprintf (dev->name, "RTL8169#%d", card_number); 1141 1142 dev->priv = (void *)(unsigned long)devno; 1143 dev->iobase = (int)pci_mem_to_phys(devno, iobase); 1144 1145 dev->init = rtl_reset; 1146 dev->halt = rtl_halt; 1147 dev->send = rtl_send; 1148 dev->recv = rtl_recv; 1149 1150 err = rtl_init(dev->iobase, dev->name, dev->enetaddr); 1151 if (err < 0) { 1152 printf(pr_fmt("failed to initialize card: %d\n"), err); 1153 free(dev); 1154 continue; 1155 } 1156 1157 eth_register (dev); 1158 1159 card_number++; 1160 } 1161 return card_number; 1162 } 1163 #endif 1164 1165 #ifdef CONFIG_DM_ETH 1166 static int rtl8169_eth_probe(struct udevice *dev) 1167 { 1168 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev); 1169 struct rtl8169_private *priv = dev_get_priv(dev); 1170 struct eth_pdata *plat = dev_get_platdata(dev); 1171 u32 iobase; 1172 int region; 1173 int ret; 1174 1175 debug("rtl8169: REALTEK RTL8169 @0x%x\n", iobase); 1176 switch (pplat->device) { 1177 case 0x8168: 1178 region = 2; 1179 break; 1180 default: 1181 region = 1; 1182 break; 1183 } 1184 dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0 + region * 4, &iobase); 1185 iobase &= ~0xf; 1186 priv->iobase = (int)dm_pci_mem_to_phys(dev, iobase); 1187 1188 ret = rtl_init(priv->iobase, dev->name, plat->enetaddr); 1189 if (ret < 0) { 1190 printf(pr_fmt("failed to initialize card: %d\n"), ret); 1191 return ret; 1192 } 1193 1194 return 0; 1195 } 1196 1197 static const struct eth_ops rtl8169_eth_ops = { 1198 .start = rtl8169_eth_start, 1199 .send = rtl8169_eth_send, 1200 .recv = rtl8169_eth_recv, 1201 .stop = rtl8169_eth_stop, 1202 }; 1203 1204 static const struct udevice_id rtl8169_eth_ids[] = { 1205 { .compatible = "realtek,rtl8169" }, 1206 { } 1207 }; 1208 1209 U_BOOT_DRIVER(eth_rtl8169) = { 1210 .name = "eth_rtl8169", 1211 .id = UCLASS_ETH, 1212 .of_match = rtl8169_eth_ids, 1213 .probe = rtl8169_eth_probe, 1214 .ops = &rtl8169_eth_ops, 1215 .priv_auto_alloc_size = sizeof(struct rtl8169_private), 1216 .platdata_auto_alloc_size = sizeof(struct eth_pdata), 1217 }; 1218 1219 U_BOOT_PCI_DEVICE(eth_rtl8169, supported); 1220 #endif 1221
