1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2016 Rockchip Electronics Co., Ltd 4 */ 5 6 #include <common.h> 7 #include <dm.h> 8 #include <errno.h> 9 #include <syscon.h> 10 #include <asm/arch/clock.h> 11 #include <asm/arch/hardware.h> 12 #include <asm/arch/grf_rk3328.h> 13 #include <asm/arch/periph.h> 14 #include <asm/io.h> 15 #include <dm/pinctrl.h> 16 17 enum { 18 /* GPIO0A_IOMUX */ 19 GPIO0A5_SEL_SHIFT = 10, 20 GPIO0A5_SEL_MASK = 3 << GPIO0A5_SEL_SHIFT, 21 GPIO0A5_I2C3_SCL = 2, 22 23 GPIO0A6_SEL_SHIFT = 12, 24 GPIO0A6_SEL_MASK = 3 << GPIO0A6_SEL_SHIFT, 25 GPIO0A6_I2C3_SDA = 2, 26 27 GPIO0A7_SEL_SHIFT = 14, 28 GPIO0A7_SEL_MASK = 3 << GPIO0A7_SEL_SHIFT, 29 GPIO0A7_EMMC_DATA0 = 2, 30 31 /* GPIO0B_IOMUX*/ 32 GPIO0B0_SEL_SHIFT = 0, 33 GPIO0B0_SEL_MASK = 3 << GPIO0B0_SEL_SHIFT, 34 GPIO0B0_GAMC_CLKTXM0 = 1, 35 36 GPIO0B4_SEL_SHIFT = 8, 37 GPIO0B4_SEL_MASK = 3 << GPIO0B4_SEL_SHIFT, 38 GPIO0B4_GAMC_TXENM0 = 1, 39 40 /* GPIO0C_IOMUX*/ 41 GPIO0C0_SEL_SHIFT = 0, 42 GPIO0C0_SEL_MASK = 3 << GPIO0C0_SEL_SHIFT, 43 GPIO0C0_GAMC_TXD1M0 = 1, 44 45 GPIO0C1_SEL_SHIFT = 2, 46 GPIO0C1_SEL_MASK = 3 << GPIO0C1_SEL_SHIFT, 47 GPIO0C1_GAMC_TXD0M0 = 1, 48 49 GPIO0C6_SEL_SHIFT = 12, 50 GPIO0C6_SEL_MASK = 3 << GPIO0C6_SEL_SHIFT, 51 GPIO0C6_GAMC_TXD2M0 = 1, 52 53 GPIO0C7_SEL_SHIFT = 14, 54 GPIO0C7_SEL_MASK = 3 << GPIO0C7_SEL_SHIFT, 55 GPIO0C7_GAMC_TXD3M0 = 1, 56 57 /* GPIO0D_IOMUX*/ 58 GPIO0D0_SEL_SHIFT = 0, 59 GPIO0D0_SEL_MASK = 3 << GPIO0D0_SEL_SHIFT, 60 GPIO0D0_GMAC_CLKM0 = 1, 61 62 GPIO0D6_SEL_SHIFT = 12, 63 GPIO0D6_SEL_MASK = 3 << GPIO0D6_SEL_SHIFT, 64 GPIO0D6_GPIO = 0, 65 GPIO0D6_SDMMC0_PWRENM1 = 3, 66 67 /* GPIO1A_IOMUX */ 68 GPIO1A0_SEL_SHIFT = 0, 69 GPIO1A0_SEL_MASK = 0x3fff << GPIO1A0_SEL_SHIFT, 70 GPIO1A0_CARD_DATA_CLK_CMD_DETN = 0x1555, 71 72 /* GPIO1B_IOMUX */ 73 GPIO1B0_SEL_SHIFT = 0, 74 GPIO1B0_SEL_MASK = 3 << GPIO1B0_SEL_SHIFT, 75 GPIO1B0_GMAC_TXD1M1 = 2, 76 77 GPIO1B1_SEL_SHIFT = 2, 78 GPIO1B1_SEL_MASK = 3 << GPIO1B1_SEL_SHIFT, 79 GPIO1B1_GMAC_TXD0M1 = 2, 80 81 GPIO1B2_SEL_SHIFT = 4, 82 GPIO1B2_SEL_MASK = 3 << GPIO1B2_SEL_SHIFT, 83 GPIO1B2_GMAC_RXD1M1 = 2, 84 85 GPIO1B3_SEL_SHIFT = 6, 86 GPIO1B3_SEL_MASK = 3 << GPIO1B3_SEL_SHIFT, 87 GPIO1B3_GMAC_RXD0M1 = 2, 88 89 GPIO1B4_SEL_SHIFT = 8, 90 GPIO1B4_SEL_MASK = 3 << GPIO1B4_SEL_SHIFT, 91 GPIO1B4_GMAC_TXCLKM1 = 2, 92 93 GPIO1B5_SEL_SHIFT = 10, 94 GPIO1B5_SEL_MASK = 3 << GPIO1B5_SEL_SHIFT, 95 GPIO1B5_GMAC_RXCLKM1 = 2, 96 97 GPIO1B6_SEL_SHIFT = 12, 98 GPIO1B6_SEL_MASK = 3 << GPIO1B6_SEL_SHIFT, 99 GPIO1B6_GMAC_RXD3M1 = 2, 100 101 GPIO1B7_SEL_SHIFT = 14, 102 GPIO1B7_SEL_MASK = 3 << GPIO1B7_SEL_SHIFT, 103 GPIO1B7_GMAC_RXD2M1 = 2, 104 105 /* GPIO1C_IOMUX */ 106 GPIO1C0_SEL_SHIFT = 0, 107 GPIO1C0_SEL_MASK = 3 << GPIO1C0_SEL_SHIFT, 108 GPIO1C0_GMAC_TXD3M1 = 2, 109 110 GPIO1C1_SEL_SHIFT = 2, 111 GPIO1C1_SEL_MASK = 3 << GPIO1C1_SEL_SHIFT, 112 GPIO1C1_GMAC_TXD2M1 = 2, 113 114 GPIO1C3_SEL_SHIFT = 6, 115 GPIO1C3_SEL_MASK = 3 << GPIO1C3_SEL_SHIFT, 116 GPIO1C3_GMAC_MDIOM1 = 2, 117 118 GPIO1C5_SEL_SHIFT = 10, 119 GPIO1C5_SEL_MASK = 3 << GPIO1C5_SEL_SHIFT, 120 GPIO1C5_GMAC_CLKM1 = 2, 121 122 GPIO1C6_SEL_SHIFT = 12, 123 GPIO1C6_SEL_MASK = 3 << GPIO1C6_SEL_SHIFT, 124 GPIO1C6_GMAC_RXDVM1 = 2, 125 126 GPIO1C7_SEL_SHIFT = 14, 127 GPIO1C7_SEL_MASK = 3 << GPIO1C7_SEL_SHIFT, 128 GPIO1C7_GMAC_MDCM1 = 2, 129 130 /* GPIO1D_IOMUX */ 131 GPIO1D1_SEL_SHIFT = 2, 132 GPIO1D1_SEL_MASK = 3 << GPIO1D1_SEL_SHIFT, 133 GPIO1D1_GMAC_TXENM1 = 2, 134 135 /* GPIO2A_IOMUX */ 136 GPIO2A0_SEL_SHIFT = 0, 137 GPIO2A0_SEL_MASK = 3 << GPIO2A0_SEL_SHIFT, 138 GPIO2A0_UART2_TX_M1 = 1, 139 140 GPIO2A1_SEL_SHIFT = 2, 141 GPIO2A1_SEL_MASK = 3 << GPIO2A1_SEL_SHIFT, 142 GPIO2A1_UART2_RX_M1 = 1, 143 144 GPIO2A2_SEL_SHIFT = 4, 145 GPIO2A2_SEL_MASK = 3 << GPIO2A2_SEL_SHIFT, 146 GPIO2A2_PWM_IR = 1, 147 148 GPIO2A4_SEL_SHIFT = 8, 149 GPIO2A4_SEL_MASK = 3 << GPIO2A4_SEL_SHIFT, 150 GPIO2A4_PWM_0 = 1, 151 GPIO2A4_I2C1_SDA, 152 153 GPIO2A5_SEL_SHIFT = 10, 154 GPIO2A5_SEL_MASK = 3 << GPIO2A5_SEL_SHIFT, 155 GPIO2A5_PWM_1 = 1, 156 GPIO2A5_I2C1_SCL, 157 158 GPIO2A6_SEL_SHIFT = 12, 159 GPIO2A6_SEL_MASK = 3 << GPIO2A6_SEL_SHIFT, 160 GPIO2A6_PWM_2 = 1, 161 162 GPIO2A7_SEL_SHIFT = 14, 163 GPIO2A7_SEL_MASK = 3 << GPIO2A7_SEL_SHIFT, 164 GPIO2A7_GPIO = 0, 165 GPIO2A7_SDMMC0_PWRENM0, 166 167 /* GPIO2BL_IOMUX */ 168 GPIO2BL0_SEL_SHIFT = 0, 169 GPIO2BL0_SEL_MASK = 0x3f << GPIO2BL0_SEL_SHIFT, 170 GPIO2BL0_SPI_CLK_TX_RX_M0 = 0x15, 171 172 GPIO2BL3_SEL_SHIFT = 6, 173 GPIO2BL3_SEL_MASK = 3 << GPIO2BL3_SEL_SHIFT, 174 GPIO2BL3_SPI_CSN0_M0 = 1, 175 176 GPIO2BL4_SEL_SHIFT = 8, 177 GPIO2BL4_SEL_MASK = 3 << GPIO2BL4_SEL_SHIFT, 178 GPIO2BL4_SPI_CSN1_M0 = 1, 179 180 GPIO2BL5_SEL_SHIFT = 10, 181 GPIO2BL5_SEL_MASK = 3 << GPIO2BL5_SEL_SHIFT, 182 GPIO2BL5_I2C2_SDA = 1, 183 184 GPIO2BL6_SEL_SHIFT = 12, 185 GPIO2BL6_SEL_MASK = 3 << GPIO2BL6_SEL_SHIFT, 186 GPIO2BL6_I2C2_SCL = 1, 187 188 /* GPIO2D_IOMUX */ 189 GPIO2D0_SEL_SHIFT = 0, 190 GPIO2D0_SEL_MASK = 3 << GPIO2D0_SEL_SHIFT, 191 GPIO2D0_I2C0_SCL = 1, 192 193 GPIO2D1_SEL_SHIFT = 2, 194 GPIO2D1_SEL_MASK = 3 << GPIO2D1_SEL_SHIFT, 195 GPIO2D1_I2C0_SDA = 1, 196 197 GPIO2D4_SEL_SHIFT = 8, 198 GPIO2D4_SEL_MASK = 0xff << GPIO2D4_SEL_SHIFT, 199 GPIO2D4_EMMC_DATA1234 = 0xaa, 200 201 /* GPIO3C_IOMUX */ 202 GPIO3C0_SEL_SHIFT = 0, 203 GPIO3C0_SEL_MASK = 0x3fff << GPIO3C0_SEL_SHIFT, 204 GPIO3C0_EMMC_DATA567_PWR_CLK_RSTN_CMD = 0x2aaa, 205 206 /* COM_IOMUX */ 207 IOMUX_SEL_UART2_SHIFT = 0, 208 IOMUX_SEL_UART2_MASK = 3 << IOMUX_SEL_UART2_SHIFT, 209 IOMUX_SEL_UART2_M0 = 0, 210 IOMUX_SEL_UART2_M1, 211 212 IOMUX_SEL_GMAC_SHIFT = 2, 213 IOMUX_SEL_GMAC_MASK = 1 << IOMUX_SEL_GMAC_SHIFT, 214 IOMUX_SEL_GMAC_M0 = 0, 215 IOMUX_SEL_GMAC_M1, 216 217 IOMUX_SEL_SPI_SHIFT = 4, 218 IOMUX_SEL_SPI_MASK = 3 << IOMUX_SEL_SPI_SHIFT, 219 IOMUX_SEL_SPI_M0 = 0, 220 IOMUX_SEL_SPI_M1, 221 IOMUX_SEL_SPI_M2, 222 223 IOMUX_SEL_SDMMC_SHIFT = 7, 224 IOMUX_SEL_SDMMC_MASK = 1 << IOMUX_SEL_SDMMC_SHIFT, 225 IOMUX_SEL_SDMMC_M0 = 0, 226 IOMUX_SEL_SDMMC_M1, 227 228 IOMUX_SEL_GMACM1_OPTIMIZATION_SHIFT = 10, 229 IOMUX_SEL_GMACM1_OPTIMIZATION_MASK = 1 << IOMUX_SEL_GMACM1_OPTIMIZATION_SHIFT, 230 IOMUX_SEL_GMACM1_OPTIMIZATION_BEFORE = 0, 231 IOMUX_SEL_GMACM1_OPTIMIZATION_AFTER, 232 233 /* GRF_GPIO1B_E */ 234 GRF_GPIO1B0_E_SHIFT = 0, 235 GRF_GPIO1B0_E_MASK = 3 << GRF_GPIO1B0_E_SHIFT, 236 GRF_GPIO1B1_E_SHIFT = 2, 237 GRF_GPIO1B1_E_MASK = 3 << GRF_GPIO1B1_E_SHIFT, 238 GRF_GPIO1B2_E_SHIFT = 4, 239 GRF_GPIO1B2_E_MASK = 3 << GRF_GPIO1B2_E_SHIFT, 240 GRF_GPIO1B3_E_SHIFT = 6, 241 GRF_GPIO1B3_E_MASK = 3 << GRF_GPIO1B3_E_SHIFT, 242 GRF_GPIO1B4_E_SHIFT = 8, 243 GRF_GPIO1B4_E_MASK = 3 << GRF_GPIO1B4_E_SHIFT, 244 GRF_GPIO1B5_E_SHIFT = 10, 245 GRF_GPIO1B5_E_MASK = 3 << GRF_GPIO1B5_E_SHIFT, 246 GRF_GPIO1B6_E_SHIFT = 12, 247 GRF_GPIO1B6_E_MASK = 3 << GRF_GPIO1B6_E_SHIFT, 248 GRF_GPIO1B7_E_SHIFT = 14, 249 GRF_GPIO1B7_E_MASK = 3 << GRF_GPIO1B7_E_SHIFT, 250 251 /* GRF_GPIO1C_E */ 252 GRF_GPIO1C0_E_SHIFT = 0, 253 GRF_GPIO1C0_E_MASK = 3 << GRF_GPIO1C0_E_SHIFT, 254 GRF_GPIO1C1_E_SHIFT = 2, 255 GRF_GPIO1C1_E_MASK = 3 << GRF_GPIO1C1_E_SHIFT, 256 GRF_GPIO1C3_E_SHIFT = 6, 257 GRF_GPIO1C3_E_MASK = 3 << GRF_GPIO1C3_E_SHIFT, 258 GRF_GPIO1C5_E_SHIFT = 10, 259 GRF_GPIO1C5_E_MASK = 3 << GRF_GPIO1C5_E_SHIFT, 260 GRF_GPIO1C6_E_SHIFT = 12, 261 GRF_GPIO1C6_E_MASK = 3 << GRF_GPIO1C6_E_SHIFT, 262 GRF_GPIO1C7_E_SHIFT = 14, 263 GRF_GPIO1C7_E_MASK = 3 << GRF_GPIO1C7_E_SHIFT, 264 265 /* GRF_GPIO1D_E */ 266 GRF_GPIO1D1_E_SHIFT = 2, 267 GRF_GPIO1D1_E_MASK = 3 << GRF_GPIO1D1_E_SHIFT, 268 }; 269 270 /* GPIO Bias drive strength settings */ 271 enum GPIO_BIAS { 272 GPIO_BIAS_2MA = 0, 273 GPIO_BIAS_4MA, 274 GPIO_BIAS_8MA, 275 GPIO_BIAS_12MA, 276 }; 277 278 struct rk3328_pinctrl_priv { 279 struct rk3328_grf_regs *grf; 280 }; 281 282 static void pinctrl_rk3328_pwm_config(struct rk3328_grf_regs *grf, int pwm_id) 283 { 284 switch (pwm_id) { 285 case PERIPH_ID_PWM0: 286 rk_clrsetreg(&grf->gpio2a_iomux, 287 GPIO2A4_SEL_MASK, 288 GPIO2A4_PWM_0 << GPIO2A4_SEL_SHIFT); 289 break; 290 case PERIPH_ID_PWM1: 291 rk_clrsetreg(&grf->gpio2a_iomux, 292 GPIO2A5_SEL_MASK, 293 GPIO2A5_PWM_1 << GPIO2A5_SEL_SHIFT); 294 break; 295 case PERIPH_ID_PWM2: 296 rk_clrsetreg(&grf->gpio2a_iomux, 297 GPIO2A6_SEL_MASK, 298 GPIO2A6_PWM_2 << GPIO2A6_SEL_SHIFT); 299 break; 300 case PERIPH_ID_PWM3: 301 rk_clrsetreg(&grf->gpio2a_iomux, 302 GPIO2A2_SEL_MASK, 303 GPIO2A2_PWM_IR << GPIO2A2_SEL_SHIFT); 304 break; 305 default: 306 debug("pwm id = %d iomux error!\n", pwm_id); 307 break; 308 } 309 } 310 311 static void pinctrl_rk3328_i2c_config(struct rk3328_grf_regs *grf, int i2c_id) 312 { 313 switch (i2c_id) { 314 case PERIPH_ID_I2C0: 315 rk_clrsetreg(&grf->gpio2d_iomux, 316 GPIO2D0_SEL_MASK | GPIO2D1_SEL_MASK, 317 GPIO2D0_I2C0_SCL << GPIO2D0_SEL_SHIFT | 318 GPIO2D1_I2C0_SDA << GPIO2D1_SEL_SHIFT); 319 break; 320 case PERIPH_ID_I2C1: 321 rk_clrsetreg(&grf->gpio2a_iomux, 322 GPIO2A4_SEL_MASK | GPIO2A5_SEL_MASK, 323 GPIO2A5_I2C1_SCL << GPIO2A5_SEL_SHIFT | 324 GPIO2A4_I2C1_SDA << GPIO2A4_SEL_SHIFT); 325 break; 326 case PERIPH_ID_I2C2: 327 rk_clrsetreg(&grf->gpio2bl_iomux, 328 GPIO2BL5_SEL_MASK | GPIO2BL6_SEL_MASK, 329 GPIO2BL6_I2C2_SCL << GPIO2BL6_SEL_SHIFT | 330 GPIO2BL5_I2C2_SDA << GPIO2BL5_SEL_SHIFT); 331 break; 332 case PERIPH_ID_I2C3: 333 rk_clrsetreg(&grf->gpio0a_iomux, 334 GPIO0A5_SEL_MASK | GPIO0A6_SEL_MASK, 335 GPIO0A5_I2C3_SCL << GPIO0A5_SEL_SHIFT | 336 GPIO0A6_I2C3_SDA << GPIO0A6_SEL_SHIFT); 337 break; 338 default: 339 debug("i2c id = %d iomux error!\n", i2c_id); 340 break; 341 } 342 } 343 344 static void pinctrl_rk3328_lcdc_config(struct rk3328_grf_regs *grf, int lcd_id) 345 { 346 switch (lcd_id) { 347 case PERIPH_ID_LCDC0: 348 break; 349 default: 350 debug("lcdc id = %d iomux error!\n", lcd_id); 351 break; 352 } 353 } 354 355 static int pinctrl_rk3328_spi_config(struct rk3328_grf_regs *grf, 356 enum periph_id spi_id, int cs) 357 { 358 u32 com_iomux = readl(&grf->com_iomux); 359 360 if ((com_iomux & IOMUX_SEL_SPI_MASK) != 361 IOMUX_SEL_SPI_M0 << IOMUX_SEL_SPI_SHIFT) { 362 debug("driver do not support iomux other than m0\n"); 363 goto err; 364 } 365 366 switch (spi_id) { 367 case PERIPH_ID_SPI0: 368 switch (cs) { 369 case 0: 370 rk_clrsetreg(&grf->gpio2bl_iomux, 371 GPIO2BL3_SEL_MASK, 372 GPIO2BL3_SPI_CSN0_M0 373 << GPIO2BL3_SEL_SHIFT); 374 break; 375 case 1: 376 rk_clrsetreg(&grf->gpio2bl_iomux, 377 GPIO2BL4_SEL_MASK, 378 GPIO2BL4_SPI_CSN1_M0 379 << GPIO2BL4_SEL_SHIFT); 380 break; 381 default: 382 goto err; 383 } 384 rk_clrsetreg(&grf->gpio2bl_iomux, 385 GPIO2BL0_SEL_MASK, 386 GPIO2BL0_SPI_CLK_TX_RX_M0 << GPIO2BL0_SEL_SHIFT); 387 break; 388 default: 389 goto err; 390 } 391 392 return 0; 393 err: 394 debug("rkspi: periph%d cs=%d not supported", spi_id, cs); 395 return -ENOENT; 396 } 397 398 static void pinctrl_rk3328_uart_config(struct rk3328_grf_regs *grf, int uart_id) 399 { 400 u32 com_iomux = readl(&grf->com_iomux); 401 402 switch (uart_id) { 403 case PERIPH_ID_UART2: 404 break; 405 if (com_iomux & IOMUX_SEL_UART2_MASK) 406 rk_clrsetreg(&grf->gpio2a_iomux, 407 GPIO2A0_SEL_MASK | GPIO2A1_SEL_MASK, 408 GPIO2A0_UART2_TX_M1 << GPIO2A0_SEL_SHIFT | 409 GPIO2A1_UART2_RX_M1 << GPIO2A1_SEL_SHIFT); 410 411 break; 412 case PERIPH_ID_UART0: 413 case PERIPH_ID_UART1: 414 case PERIPH_ID_UART3: 415 case PERIPH_ID_UART4: 416 default: 417 debug("uart id = %d iomux error!\n", uart_id); 418 break; 419 } 420 } 421 422 static void pinctrl_rk3328_sdmmc_config(struct rk3328_grf_regs *grf, 423 int mmc_id) 424 { 425 u32 com_iomux = readl(&grf->com_iomux); 426 427 switch (mmc_id) { 428 case PERIPH_ID_EMMC: 429 rk_clrsetreg(&grf->gpio0a_iomux, 430 GPIO0A7_SEL_MASK, 431 GPIO0A7_EMMC_DATA0 << GPIO0A7_SEL_SHIFT); 432 rk_clrsetreg(&grf->gpio2d_iomux, 433 GPIO2D4_SEL_MASK, 434 GPIO2D4_EMMC_DATA1234 << GPIO2D4_SEL_SHIFT); 435 rk_clrsetreg(&grf->gpio3c_iomux, 436 GPIO3C0_SEL_MASK, 437 GPIO3C0_EMMC_DATA567_PWR_CLK_RSTN_CMD 438 << GPIO3C0_SEL_SHIFT); 439 break; 440 case PERIPH_ID_SDCARD: 441 /* SDMMC_PWREN use GPIO and init as regulator-fiexed */ 442 if (com_iomux & IOMUX_SEL_SDMMC_MASK) 443 rk_clrsetreg(&grf->gpio0d_iomux, 444 GPIO0D6_SEL_MASK, 445 GPIO0D6_GPIO << GPIO0D6_SEL_SHIFT); 446 else 447 rk_clrsetreg(&grf->gpio2a_iomux, 448 GPIO2A7_SEL_MASK, 449 GPIO2A7_GPIO << GPIO2A7_SEL_SHIFT); 450 rk_clrsetreg(&grf->gpio1a_iomux, 451 GPIO1A0_SEL_MASK, 452 GPIO1A0_CARD_DATA_CLK_CMD_DETN 453 << GPIO1A0_SEL_SHIFT); 454 break; 455 default: 456 debug("mmc id = %d iomux error!\n", mmc_id); 457 break; 458 } 459 } 460 461 #if CONFIG_IS_ENABLED(GMAC_ROCKCHIP) 462 static void pinctrl_rk3328_gmac_config(struct rk3328_grf_regs *grf, int gmac_id) 463 { 464 switch (gmac_id) { 465 case PERIPH_ID_GMAC: 466 /* set rgmii m1 pins mux */ 467 rk_clrsetreg(&grf->gpio1b_iomux, 468 GPIO1B0_SEL_MASK | 469 GPIO1B1_SEL_MASK | 470 GPIO1B2_SEL_MASK | 471 GPIO1B3_SEL_MASK | 472 GPIO1B4_SEL_MASK | 473 GPIO1B5_SEL_MASK | 474 GPIO1B6_SEL_MASK | 475 GPIO1B7_SEL_MASK, 476 GPIO1B0_GMAC_TXD1M1 << GPIO1B0_SEL_SHIFT | 477 GPIO1B1_GMAC_TXD0M1 << GPIO1B1_SEL_SHIFT | 478 GPIO1B2_GMAC_RXD1M1 << GPIO1B2_SEL_SHIFT | 479 GPIO1B3_GMAC_RXD0M1 << GPIO1B3_SEL_SHIFT | 480 GPIO1B4_GMAC_TXCLKM1 << GPIO1B4_SEL_SHIFT | 481 GPIO1B5_GMAC_RXCLKM1 << GPIO1B5_SEL_SHIFT | 482 GPIO1B6_GMAC_RXD3M1 << GPIO1B6_SEL_SHIFT | 483 GPIO1B7_GMAC_RXD2M1 << GPIO1B7_SEL_SHIFT); 484 485 rk_clrsetreg(&grf->gpio1c_iomux, 486 GPIO1C0_SEL_MASK | 487 GPIO1C1_SEL_MASK | 488 GPIO1C3_SEL_MASK | 489 GPIO1C5_SEL_MASK | 490 GPIO1C6_SEL_MASK | 491 GPIO1C7_SEL_MASK, 492 GPIO1C0_GMAC_TXD3M1 << GPIO1C0_SEL_SHIFT | 493 GPIO1C1_GMAC_TXD2M1 << GPIO1C1_SEL_SHIFT | 494 GPIO1C3_GMAC_MDIOM1 << GPIO1C3_SEL_SHIFT | 495 GPIO1C5_GMAC_CLKM1 << GPIO1C5_SEL_SHIFT | 496 GPIO1C6_GMAC_RXDVM1 << GPIO1C6_SEL_SHIFT | 497 GPIO1C7_GMAC_MDCM1 << GPIO1C7_SEL_SHIFT); 498 499 rk_clrsetreg(&grf->gpio1d_iomux, 500 GPIO1D1_SEL_MASK, 501 GPIO1D1_GMAC_TXENM1 << GPIO1D1_SEL_SHIFT); 502 503 /* set rgmii m0 tx pins mux */ 504 rk_clrsetreg(&grf->gpio0b_iomux, 505 GPIO0B0_SEL_MASK | 506 GPIO0B4_SEL_MASK, 507 GPIO0B0_GAMC_CLKTXM0 << GPIO0B0_SEL_SHIFT | 508 GPIO0B4_GAMC_TXENM0 << GPIO0B4_SEL_SHIFT); 509 510 rk_clrsetreg(&grf->gpio0c_iomux, 511 GPIO0C0_SEL_MASK | 512 GPIO0C1_SEL_MASK | 513 GPIO0C6_SEL_MASK | 514 GPIO0C7_SEL_MASK, 515 GPIO0C0_GAMC_TXD1M0 << GPIO0C0_SEL_SHIFT | 516 GPIO0C1_GAMC_TXD0M0 << GPIO0C1_SEL_SHIFT | 517 GPIO0C6_GAMC_TXD2M0 << GPIO0C6_SEL_SHIFT | 518 GPIO0C7_GAMC_TXD3M0 << GPIO0C7_SEL_SHIFT); 519 520 rk_clrsetreg(&grf->gpio0d_iomux, 521 GPIO0D0_SEL_MASK, 522 GPIO0D0_GMAC_CLKM0 << GPIO0D0_SEL_SHIFT); 523 524 /* set com mux */ 525 rk_clrsetreg(&grf->com_iomux, 526 IOMUX_SEL_GMAC_MASK | 527 IOMUX_SEL_GMACM1_OPTIMIZATION_MASK, 528 IOMUX_SEL_GMAC_M1 << IOMUX_SEL_GMAC_SHIFT | 529 IOMUX_SEL_GMACM1_OPTIMIZATION_AFTER << 530 IOMUX_SEL_GMACM1_OPTIMIZATION_SHIFT); 531 532 /* 533 * set rgmii m1 tx pins to 12ma drive-strength, 534 * and clean others to 2ma. 535 */ 536 rk_clrsetreg(&grf->gpio1b_e, 537 GRF_GPIO1B0_E_MASK | 538 GRF_GPIO1B1_E_MASK | 539 GRF_GPIO1B2_E_MASK | 540 GRF_GPIO1B3_E_MASK | 541 GRF_GPIO1B4_E_MASK | 542 GRF_GPIO1B5_E_MASK | 543 GRF_GPIO1B6_E_MASK | 544 GRF_GPIO1B7_E_MASK, 545 GPIO_BIAS_12MA << GRF_GPIO1B0_E_SHIFT | 546 GPIO_BIAS_12MA << GRF_GPIO1B1_E_SHIFT | 547 GPIO_BIAS_2MA << GRF_GPIO1B2_E_SHIFT | 548 GPIO_BIAS_2MA << GRF_GPIO1B3_E_SHIFT | 549 GPIO_BIAS_12MA << GRF_GPIO1B4_E_SHIFT | 550 GPIO_BIAS_2MA << GRF_GPIO1B5_E_SHIFT | 551 GPIO_BIAS_2MA << GRF_GPIO1B6_E_SHIFT | 552 GPIO_BIAS_2MA << GRF_GPIO1B7_E_SHIFT); 553 554 rk_clrsetreg(&grf->gpio1c_e, 555 GRF_GPIO1C0_E_MASK | 556 GRF_GPIO1C1_E_MASK | 557 GRF_GPIO1C3_E_MASK | 558 GRF_GPIO1C5_E_MASK | 559 GRF_GPIO1C6_E_MASK | 560 GRF_GPIO1C7_E_MASK, 561 GPIO_BIAS_12MA << GRF_GPIO1C0_E_SHIFT | 562 GPIO_BIAS_12MA << GRF_GPIO1C1_E_SHIFT | 563 GPIO_BIAS_2MA << GRF_GPIO1C3_E_SHIFT | 564 GPIO_BIAS_2MA << GRF_GPIO1C5_E_SHIFT | 565 GPIO_BIAS_2MA << GRF_GPIO1C6_E_SHIFT | 566 GPIO_BIAS_2MA << GRF_GPIO1C7_E_SHIFT); 567 568 rk_clrsetreg(&grf->gpio1d_e, 569 GRF_GPIO1D1_E_MASK, 570 GPIO_BIAS_12MA << GRF_GPIO1D1_E_SHIFT); 571 break; 572 default: 573 debug("gmac id = %d iomux error!\n", gmac_id); 574 break; 575 } 576 } 577 #endif 578 579 static int rk3328_pinctrl_request(struct udevice *dev, int func, int flags) 580 { 581 struct rk3328_pinctrl_priv *priv = dev_get_priv(dev); 582 583 debug("%s: func=%x, flags=%x\n", __func__, func, flags); 584 switch (func) { 585 case PERIPH_ID_PWM0: 586 case PERIPH_ID_PWM1: 587 case PERIPH_ID_PWM2: 588 case PERIPH_ID_PWM3: 589 pinctrl_rk3328_pwm_config(priv->grf, func); 590 break; 591 case PERIPH_ID_I2C0: 592 case PERIPH_ID_I2C1: 593 case PERIPH_ID_I2C2: 594 case PERIPH_ID_I2C3: 595 pinctrl_rk3328_i2c_config(priv->grf, func); 596 break; 597 case PERIPH_ID_SPI0: 598 pinctrl_rk3328_spi_config(priv->grf, func, flags); 599 break; 600 case PERIPH_ID_UART0: 601 case PERIPH_ID_UART1: 602 case PERIPH_ID_UART2: 603 case PERIPH_ID_UART3: 604 case PERIPH_ID_UART4: 605 pinctrl_rk3328_uart_config(priv->grf, func); 606 break; 607 case PERIPH_ID_LCDC0: 608 case PERIPH_ID_LCDC1: 609 pinctrl_rk3328_lcdc_config(priv->grf, func); 610 break; 611 case PERIPH_ID_SDMMC0: 612 case PERIPH_ID_SDMMC1: 613 pinctrl_rk3328_sdmmc_config(priv->grf, func); 614 break; 615 #if CONFIG_IS_ENABLED(GMAC_ROCKCHIP) 616 case PERIPH_ID_GMAC: 617 pinctrl_rk3328_gmac_config(priv->grf, func); 618 break; 619 #endif 620 default: 621 return -EINVAL; 622 } 623 624 return 0; 625 } 626 627 static int rk3328_pinctrl_get_periph_id(struct udevice *dev, 628 struct udevice *periph) 629 { 630 u32 cell[3]; 631 int ret; 632 633 ret = dev_read_u32_array(periph, "interrupts", cell, ARRAY_SIZE(cell)); 634 if (ret < 0) 635 return -EINVAL; 636 637 switch (cell[1]) { 638 case 49: 639 return PERIPH_ID_SPI0; 640 case 50: 641 return PERIPH_ID_PWM0; 642 case 36: 643 return PERIPH_ID_I2C0; 644 case 37: /* Note strange order */ 645 return PERIPH_ID_I2C1; 646 case 38: 647 return PERIPH_ID_I2C2; 648 case 39: 649 return PERIPH_ID_I2C3; 650 case 12: 651 return PERIPH_ID_SDCARD; 652 case 14: 653 return PERIPH_ID_EMMC; 654 #if CONFIG_IS_ENABLED(GMAC_ROCKCHIP) 655 case 24: 656 return PERIPH_ID_GMAC; 657 #endif 658 } 659 660 return -ENOENT; 661 } 662 663 static int rk3328_pinctrl_set_state_simple(struct udevice *dev, 664 struct udevice *periph) 665 { 666 int func; 667 668 func = rk3328_pinctrl_get_periph_id(dev, periph); 669 if (func < 0) 670 return func; 671 672 return rk3328_pinctrl_request(dev, func, 0); 673 } 674 675 static struct pinctrl_ops rk3328_pinctrl_ops = { 676 .set_state_simple = rk3328_pinctrl_set_state_simple, 677 .request = rk3328_pinctrl_request, 678 .get_periph_id = rk3328_pinctrl_get_periph_id, 679 }; 680 681 static int rk3328_pinctrl_probe(struct udevice *dev) 682 { 683 struct rk3328_pinctrl_priv *priv = dev_get_priv(dev); 684 int ret = 0; 685 686 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 687 debug("%s: grf=%p\n", __func__, priv->grf); 688 689 return ret; 690 } 691 692 static const struct udevice_id rk3328_pinctrl_ids[] = { 693 { .compatible = "rockchip,rk3328-pinctrl" }, 694 { } 695 }; 696 697 U_BOOT_DRIVER(pinctrl_rk3328) = { 698 .name = "rockchip_rk3328_pinctrl", 699 .id = UCLASS_PINCTRL, 700 .of_match = rk3328_pinctrl_ids, 701 .priv_auto_alloc_size = sizeof(struct rk3328_pinctrl_priv), 702 .ops = &rk3328_pinctrl_ops, 703 .bind = dm_scan_fdt_dev, 704 .probe = rk3328_pinctrl_probe, 705 }; 706
