1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd 4 * Author: Andy Yan <andy.yan (at) rock-chips.com> 5 * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH 6 */ 7 8 #include <common.h> 9 #include <dm.h> 10 #include <errno.h> 11 #include <syscon.h> 12 #include <asm/io.h> 13 #include <asm/arch/clock.h> 14 #include <asm/arch/hardware.h> 15 #include <asm/arch/grf_rk3368.h> 16 #include <asm/arch/periph.h> 17 #include <dm/pinctrl.h> 18 19 /* PMUGRF_GPIO0B_IOMUX */ 20 enum { 21 GPIO0B5_SHIFT = 10, 22 GPIO0B5_MASK = GENMASK(GPIO0B5_SHIFT + 1, GPIO0B5_SHIFT), 23 GPIO0B5_GPIO = 0, 24 GPIO0B5_SPI2_CSN0 = (2 << GPIO0B5_SHIFT), 25 26 GPIO0B4_SHIFT = 8, 27 GPIO0B4_MASK = GENMASK(GPIO0B4_SHIFT + 1, GPIO0B4_SHIFT), 28 GPIO0B4_GPIO = 0, 29 GPIO0B4_SPI2_CLK = (2 << GPIO0B4_SHIFT), 30 31 GPIO0B3_SHIFT = 6, 32 GPIO0B3_MASK = GENMASK(GPIO0B3_SHIFT + 1, GPIO0B3_SHIFT), 33 GPIO0B3_GPIO = 0, 34 GPIO0B3_SPI2_TXD = (2 << GPIO0B3_SHIFT), 35 36 GPIO0B2_SHIFT = 4, 37 GPIO0B2_MASK = GENMASK(GPIO0B2_SHIFT + 1, GPIO0B2_SHIFT), 38 GPIO0B2_GPIO = 0, 39 GPIO0B2_SPI2_RXD = (2 << GPIO0B2_SHIFT), 40 }; 41 42 /*GRF_GPIO0C_IOMUX*/ 43 enum { 44 GPIO0C7_SHIFT = 14, 45 GPIO0C7_MASK = GENMASK(GPIO0C7_SHIFT + 1, GPIO0C7_SHIFT), 46 GPIO0C7_GPIO = 0, 47 GPIO0C7_LCDC_D19 = (1 << GPIO0C7_SHIFT), 48 GPIO0C7_TRACE_D9 = (2 << GPIO0C7_SHIFT), 49 GPIO0C7_UART1_RTSN = (3 << GPIO0C7_SHIFT), 50 51 GPIO0C6_SHIFT = 12, 52 GPIO0C6_MASK = GENMASK(GPIO0C6_SHIFT + 1, GPIO0C6_SHIFT), 53 GPIO0C6_GPIO = 0, 54 GPIO0C6_LCDC_D18 = (1 << GPIO0C6_SHIFT), 55 GPIO0C6_TRACE_D8 = (2 << GPIO0C6_SHIFT), 56 GPIO0C6_UART1_CTSN = (3 << GPIO0C6_SHIFT), 57 58 GPIO0C5_SHIFT = 10, 59 GPIO0C5_MASK = GENMASK(GPIO0C5_SHIFT + 1, GPIO0C5_SHIFT), 60 GPIO0C5_GPIO = 0, 61 GPIO0C5_LCDC_D17 = (1 << GPIO0C5_SHIFT), 62 GPIO0C5_TRACE_D7 = (2 << GPIO0C5_SHIFT), 63 GPIO0C5_UART1_SOUT = (3 << GPIO0C5_SHIFT), 64 65 GPIO0C4_SHIFT = 8, 66 GPIO0C4_MASK = GENMASK(GPIO0C4_SHIFT + 1, GPIO0C4_SHIFT), 67 GPIO0C4_GPIO = 0, 68 GPIO0C4_LCDC_D16 = (1 << GPIO0C4_SHIFT), 69 GPIO0C4_TRACE_D6 = (2 << GPIO0C4_SHIFT), 70 GPIO0C4_UART1_SIN = (3 << GPIO0C4_SHIFT), 71 72 GPIO0C3_SHIFT = 6, 73 GPIO0C3_MASK = GENMASK(GPIO0C3_SHIFT + 1, GPIO0C3_SHIFT), 74 GPIO0C3_GPIO = 0, 75 GPIO0C3_LCDC_D15 = (1 << GPIO0C3_SHIFT), 76 GPIO0C3_TRACE_D5 = (2 << GPIO0C3_SHIFT), 77 GPIO0C3_MCU_JTAG_TDO = (3 << GPIO0C3_SHIFT), 78 79 GPIO0C2_SHIFT = 4, 80 GPIO0C2_MASK = GENMASK(GPIO0C2_SHIFT + 1, GPIO0C2_SHIFT), 81 GPIO0C2_GPIO = 0, 82 GPIO0C2_LCDC_D14 = (1 << GPIO0C2_SHIFT), 83 GPIO0C2_TRACE_D4 = (2 << GPIO0C2_SHIFT), 84 GPIO0C2_MCU_JTAG_TDI = (3 << GPIO0C2_SHIFT), 85 86 GPIO0C1_SHIFT = 2, 87 GPIO0C1_MASK = GENMASK(GPIO0C1_SHIFT + 1, GPIO0C1_SHIFT), 88 GPIO0C1_GPIO = 0, 89 GPIO0C1_LCDC_D13 = (1 << GPIO0C1_SHIFT), 90 GPIO0C1_TRACE_D3 = (2 << GPIO0C1_SHIFT), 91 GPIO0C1_MCU_JTAG_TRTSN = (3 << GPIO0C1_SHIFT), 92 93 GPIO0C0_SHIFT = 0, 94 GPIO0C0_MASK = GENMASK(GPIO0C0_SHIFT + 1, GPIO0C0_SHIFT), 95 GPIO0C0_GPIO = 0, 96 GPIO0C0_LCDC_D12 = (1 << GPIO0C0_SHIFT), 97 GPIO0C0_TRACE_D2 = (2 << GPIO0C0_SHIFT), 98 GPIO0C0_MCU_JTAG_TDO = (3 << GPIO0C0_SHIFT), 99 }; 100 101 /*GRF_GPIO0D_IOMUX*/ 102 enum { 103 GPIO0D7_SHIFT = 14, 104 GPIO0D7_MASK = GENMASK(GPIO0D7_SHIFT + 1, GPIO0D7_SHIFT), 105 GPIO0D7_GPIO = 0, 106 GPIO0D7_LCDC_DCLK = (1 << GPIO0D7_SHIFT), 107 GPIO0D7_TRACE_CTL = (2 << GPIO0D7_SHIFT), 108 GPIO0D7_PMU_DEBUG5 = (3 << GPIO0D7_SHIFT), 109 110 GPIO0D6_SHIFT = 12, 111 GPIO0D6_MASK = GENMASK(GPIO0D6_SHIFT + 1, GPIO0D6_SHIFT), 112 GPIO0D6_GPIO = 0, 113 GPIO0D6_LCDC_DEN = (1 << GPIO0D6_SHIFT), 114 GPIO0D6_TRACE_CLK = (2 << GPIO0D6_SHIFT), 115 GPIO0D6_PMU_DEBUG4 = (3 << GPIO0D6_SHIFT), 116 117 GPIO0D5_SHIFT = 10, 118 GPIO0D5_MASK = GENMASK(GPIO0D5_SHIFT + 1, GPIO0D5_SHIFT), 119 GPIO0D5_GPIO = 0, 120 GPIO0D5_LCDC_VSYNC = (1 << GPIO0D5_SHIFT), 121 GPIO0D5_TRACE_D15 = (2 << GPIO0D5_SHIFT), 122 GPIO0D5_PMU_DEBUG3 = (3 << GPIO0D5_SHIFT), 123 124 GPIO0D4_SHIFT = 8, 125 GPIO0D4_MASK = GENMASK(GPIO0D4_SHIFT + 1, GPIO0D4_SHIFT), 126 GPIO0D4_GPIO = 0, 127 GPIO0D4_LCDC_HSYNC = (1 << GPIO0D4_SHIFT), 128 GPIO0D4_TRACE_D14 = (2 << GPIO0D4_SHIFT), 129 GPIO0D4_PMU_DEBUG2 = (3 << GPIO0D4_SHIFT), 130 131 GPIO0D3_SHIFT = 6, 132 GPIO0D3_MASK = GENMASK(GPIO0D3_SHIFT + 1, GPIO0D3_SHIFT), 133 GPIO0D3_GPIO = 0, 134 GPIO0D3_LCDC_D23 = (1 << GPIO0D3_SHIFT), 135 GPIO0D3_TRACE_D13 = (2 << GPIO0D3_SHIFT), 136 GPIO0D3_UART4_SIN = (3 << GPIO0D3_SHIFT), 137 138 GPIO0D2_SHIFT = 4, 139 GPIO0D2_MASK = GENMASK(GPIO0D2_SHIFT + 1, GPIO0D2_SHIFT), 140 GPIO0D2_GPIO = 0, 141 GPIO0D2_LCDC_D22 = (1 << GPIO0D2_SHIFT), 142 GPIO0D2_TRACE_D12 = (2 << GPIO0D2_SHIFT), 143 GPIO0D2_UART4_SOUT = (3 << GPIO0D2_SHIFT), 144 145 GPIO0D1_SHIFT = 2, 146 GPIO0D1_MASK = GENMASK(GPIO0D1_SHIFT + 1, GPIO0D1_SHIFT), 147 GPIO0D1_GPIO = 0, 148 GPIO0D1_LCDC_D21 = (1 << GPIO0D1_SHIFT), 149 GPIO0D1_TRACE_D11 = (2 << GPIO0D1_SHIFT), 150 GPIO0D1_UART4_RTSN = (3 << GPIO0D1_SHIFT), 151 152 GPIO0D0_SHIFT = 0, 153 GPIO0D0_MASK = GENMASK(GPIO0D0_SHIFT + 1, GPIO0D0_SHIFT), 154 GPIO0D0_GPIO = 0, 155 GPIO0D0_LCDC_D20 = (1 << GPIO0D0_SHIFT), 156 GPIO0D0_TRACE_D10 = (2 << GPIO0D0_SHIFT), 157 GPIO0D0_UART4_CTSN = (3 << GPIO0D0_SHIFT), 158 }; 159 160 /*GRF_GPIO2A_IOMUX*/ 161 enum { 162 GPIO2A7_SHIFT = 14, 163 GPIO2A7_MASK = GENMASK(GPIO2A7_SHIFT + 1, GPIO2A7_SHIFT), 164 GPIO2A7_GPIO = 0, 165 GPIO2A7_SDMMC0_D2 = (1 << GPIO2A7_SHIFT), 166 GPIO2A7_JTAG_TCK = (2 << GPIO2A7_SHIFT), 167 168 GPIO2A6_SHIFT = 12, 169 GPIO2A6_MASK = GENMASK(GPIO2A6_SHIFT + 1, GPIO2A6_SHIFT), 170 GPIO2A6_GPIO = 0, 171 GPIO2A6_SDMMC0_D1 = (1 << GPIO2A6_SHIFT), 172 GPIO2A6_UART2_SIN = (2 << GPIO2A6_SHIFT), 173 174 GPIO2A5_SHIFT = 10, 175 GPIO2A5_MASK = GENMASK(GPIO2A5_SHIFT + 1, GPIO2A5_SHIFT), 176 GPIO2A5_GPIO = 0, 177 GPIO2A5_SDMMC0_D0 = (1 << GPIO2A5_SHIFT), 178 GPIO2A5_UART2_SOUT = (2 << GPIO2A5_SHIFT), 179 180 GPIO2A4_SHIFT = 8, 181 GPIO2A4_MASK = GENMASK(GPIO2A4_SHIFT + 1, GPIO2A4_SHIFT), 182 GPIO2A4_GPIO = 0, 183 GPIO2A4_FLASH_DQS = (1 << GPIO2A4_SHIFT), 184 GPIO2A4_EMMC_CLKOUT = (2 << GPIO2A4_SHIFT), 185 186 GPIO2A3_SHIFT = 6, 187 GPIO2A3_MASK = GENMASK(GPIO2A3_SHIFT + 1, GPIO2A3_SHIFT), 188 GPIO2A3_GPIO = 0, 189 GPIO2A3_FLASH_CSN3 = (1 << GPIO2A3_SHIFT), 190 GPIO2A3_EMMC_RSTNOUT = (2 << GPIO2A3_SHIFT), 191 192 GPIO2A2_SHIFT = 4, 193 GPIO2A2_MASK = GENMASK(GPIO2A2_SHIFT + 1, GPIO2A2_SHIFT), 194 GPIO2A2_GPIO = 0, 195 GPIO2A2_FLASH_CSN2 = (1 << GPIO2A2_SHIFT), 196 197 GPIO2A1_SHIFT = 2, 198 GPIO2A1_MASK = GENMASK(GPIO2A1_SHIFT + 1, GPIO2A1_SHIFT), 199 GPIO2A1_GPIO = 0, 200 GPIO2A1_FLASH_CSN1 = (1 << GPIO2A1_SHIFT), 201 202 GPIO2A0_SHIFT = 0, 203 GPIO2A0_MASK = GENMASK(GPIO2A0_SHIFT + 1, GPIO2A0_SHIFT), 204 GPIO2A0_GPIO = 0, 205 GPIO2A0_FLASH_CSN0 = (1 << GPIO2A0_SHIFT), 206 }; 207 208 /*GRF_GPIO2B_IOMUX*/ 209 enum { 210 GPIO2B3_SHIFT = 6, 211 GPIO2B3_MASK = GENMASK(GPIO2B3_SHIFT + 1, GPIO2B3_SHIFT), 212 GPIO2B3_GPIO = 0, 213 GPIO2B3_SDMMC0_DTECTN = (1 << GPIO2B3_SHIFT), 214 215 GPIO2B2_SHIFT = 4, 216 GPIO2B2_MASK = GENMASK(GPIO2B2_SHIFT + 1, GPIO2B2_SHIFT), 217 GPIO2B2_GPIO = 0, 218 GPIO2B2_SDMMC0_CMD = (1 << GPIO2B2_SHIFT), 219 220 GPIO2B1_SHIFT = 2, 221 GPIO2B1_MASK = GENMASK(GPIO2B1_SHIFT + 1, GPIO2B1_SHIFT), 222 GPIO2B1_GPIO = 0, 223 GPIO2B1_SDMMC0_CLKOUT = (1 << GPIO2B1_SHIFT), 224 225 GPIO2B0_SHIFT = 0, 226 GPIO2B0_MASK = GENMASK(GPIO2B0_SHIFT + 1, GPIO2B0_SHIFT), 227 GPIO2B0_GPIO = 0, 228 GPIO2B0_SDMMC0_D3 = (1 << GPIO2B0_SHIFT), 229 }; 230 231 /*GRF_GPIO2D_IOMUX*/ 232 enum { 233 GPIO2D7_SHIFT = 14, 234 GPIO2D7_MASK = GENMASK(GPIO2D7_SHIFT + 1, GPIO2D7_SHIFT), 235 GPIO2D7_GPIO = 0, 236 GPIO2D7_SDIO0_D3 = (1 << GPIO2D7_SHIFT), 237 238 GPIO2D6_SHIFT = 12, 239 GPIO2D6_MASK = GENMASK(GPIO2D6_SHIFT + 1, GPIO2D6_SHIFT), 240 GPIO2D6_GPIO = 0, 241 GPIO2D6_SDIO0_D2 = (1 << GPIO2D6_SHIFT), 242 243 GPIO2D5_SHIFT = 10, 244 GPIO2D5_MASK = GENMASK(GPIO2D5_SHIFT + 1, GPIO2D5_SHIFT), 245 GPIO2D5_GPIO = 0, 246 GPIO2D5_SDIO0_D1 = (1 << GPIO2D5_SHIFT), 247 248 GPIO2D4_SHIFT = 8, 249 GPIO2D4_MASK = GENMASK(GPIO2D4_SHIFT + 1, GPIO2D4_SHIFT), 250 GPIO2D4_GPIO = 0, 251 GPIO2D4_SDIO0_D0 = (1 << GPIO2D4_SHIFT), 252 253 GPIO2D3_SHIFT = 6, 254 GPIO2D3_MASK = GENMASK(GPIO2D3_SHIFT + 1, GPIO2D3_SHIFT), 255 GPIO2D3_GPIO = 0, 256 GPIO2D3_UART0_RTS0 = (1 << GPIO2D3_SHIFT), 257 258 GPIO2D2_SHIFT = 4, 259 GPIO2D2_MASK = GENMASK(GPIO2D2_SHIFT + 1, GPIO2D2_SHIFT), 260 GPIO2D2_GPIO = 0, 261 GPIO2D2_UART0_CTS0 = (1 << GPIO2D2_SHIFT), 262 263 GPIO2D1_SHIFT = 2, 264 GPIO2D1_MASK = GENMASK(GPIO2D1_SHIFT + 1, GPIO2D1_SHIFT), 265 GPIO2D1_GPIO = 0, 266 GPIO2D1_UART0_SOUT = (1 << GPIO2D1_SHIFT), 267 268 GPIO2D0_SHIFT = 0, 269 GPIO2D0_MASK = GENMASK(GPIO2D0_SHIFT + 1, GPIO2D0_SHIFT), 270 GPIO2D0_GPIO = 0, 271 GPIO2D0_UART0_SIN = (1 << GPIO2D0_SHIFT), 272 }; 273 274 /* GRF_GPIO1B_IOMUX */ 275 enum { 276 GPIO1B7_SHIFT = 14, 277 GPIO1B7_MASK = GENMASK(GPIO1B7_SHIFT + 1, GPIO1B7_SHIFT), 278 GPIO1B7_GPIO = 0, 279 GPIO1B7_SPI1_CSN0 = (2 << GPIO1B7_SHIFT), 280 281 GPIO1B6_SHIFT = 12, 282 GPIO1B6_MASK = GENMASK(GPIO1B6_SHIFT + 1, GPIO1B6_SHIFT), 283 GPIO1B6_GPIO = 0, 284 GPIO1B6_SPI1_CLK = (2 << GPIO1B6_SHIFT), 285 }; 286 287 /* GRF_GPIO1C_IOMUX */ 288 enum { 289 GPIO1C7_SHIFT = 14, 290 GPIO1C7_MASK = GENMASK(GPIO1C7_SHIFT + 1, GPIO1C7_SHIFT), 291 GPIO1C7_GPIO = 0, 292 GPIO1C7_EMMC_DATA5 = (2 << GPIO1C7_SHIFT), 293 GPIO1C7_SPI0_TXD = (3 << GPIO1C7_SHIFT), 294 295 GPIO1C6_SHIFT = 12, 296 GPIO1C6_MASK = GENMASK(GPIO1C6_SHIFT + 1, GPIO1C6_SHIFT), 297 GPIO1C6_GPIO = 0, 298 GPIO1C6_EMMC_DATA4 = (2 << GPIO1C6_SHIFT), 299 GPIO1C6_SPI0_RXD = (3 << GPIO1C6_SHIFT), 300 301 GPIO1C5_SHIFT = 10, 302 GPIO1C5_MASK = GENMASK(GPIO1C5_SHIFT + 1, GPIO1C5_SHIFT), 303 GPIO1C5_GPIO = 0, 304 GPIO1C5_EMMC_DATA3 = (2 << GPIO1C5_SHIFT), 305 306 GPIO1C4_SHIFT = 8, 307 GPIO1C4_MASK = GENMASK(GPIO1C4_SHIFT + 1, GPIO1C4_SHIFT), 308 GPIO1C4_GPIO = 0, 309 GPIO1C4_EMMC_DATA2 = (2 << GPIO1C4_SHIFT), 310 311 GPIO1C3_SHIFT = 6, 312 GPIO1C3_MASK = GENMASK(GPIO1C3_SHIFT + 1, GPIO1C3_SHIFT), 313 GPIO1C3_GPIO = 0, 314 GPIO1C3_EMMC_DATA1 = (2 << GPIO1C3_SHIFT), 315 316 GPIO1C2_SHIFT = 4, 317 GPIO1C2_MASK = GENMASK(GPIO1C2_SHIFT + 1, GPIO1C2_SHIFT), 318 GPIO1C2_GPIO = 0, 319 GPIO1C2_EMMC_DATA0 = (2 << GPIO1C2_SHIFT), 320 321 GPIO1C1_SHIFT = 2, 322 GPIO1C1_MASK = GENMASK(GPIO1C1_SHIFT + 1, GPIO1C1_SHIFT), 323 GPIO1C1_GPIO = 0, 324 GPIO1C1_SPI1_RXD = (2 << GPIO1C1_SHIFT), 325 326 GPIO1C0_SHIFT = 0, 327 GPIO1C0_MASK = GENMASK(GPIO1C0_SHIFT + 1, GPIO1C0_SHIFT), 328 GPIO1C0_GPIO = 0, 329 GPIO1C0_SPI1_TXD = (2 << GPIO1C0_SHIFT), 330 }; 331 332 /* GRF_GPIO1D_IOMUX*/ 333 enum { 334 GPIO1D5_SHIFT = 10, 335 GPIO1D5_MASK = GENMASK(GPIO1D5_SHIFT + 1, GPIO1D5_SHIFT), 336 GPIO1D5_GPIO = 0, 337 GPIO1D5_SPI0_CLK = (2 << GPIO1D5_SHIFT), 338 339 GPIO1D3_SHIFT = 6, 340 GPIO1D3_MASK = GENMASK(GPIO1D3_SHIFT + 1, GPIO1D3_SHIFT), 341 GPIO1D3_GPIO = 0, 342 GPIO1D3_EMMC_PWREN = (2 << GPIO1D3_SHIFT), 343 344 GPIO1D2_SHIFT = 4, 345 GPIO1D2_MASK = GENMASK(GPIO1D2_SHIFT + 1, GPIO1D2_SHIFT), 346 GPIO1D2_GPIO = 0, 347 GPIO1D2_EMMC_CMD = (2 << GPIO1D2_SHIFT), 348 349 GPIO1D1_SHIFT = 2, 350 GPIO1D1_MASK = GENMASK(GPIO1D1_SHIFT + 1, GPIO1D1_SHIFT), 351 GPIO1D1_GPIO = 0, 352 GPIO1D1_EMMC_DATA7 = (2 << GPIO1D1_SHIFT), 353 GPIO1D1_SPI0_CSN1 = (3 << GPIO1D1_SHIFT), 354 355 GPIO1D0_SHIFT = 0, 356 GPIO1D0_MASK = GENMASK(GPIO1D0_SHIFT + 1, GPIO1D0_SHIFT), 357 GPIO1D0_GPIO = 0, 358 GPIO1D0_EMMC_DATA6 = (2 << GPIO1D0_SHIFT), 359 GPIO1D0_SPI0_CSN0 = (3 << GPIO1D0_SHIFT), 360 }; 361 362 363 /*GRF_GPIO3B_IOMUX*/ 364 enum { 365 GPIO3B7_SHIFT = 14, 366 GPIO3B7_MASK = GENMASK(GPIO3B7_SHIFT + 1, GPIO3B7_SHIFT), 367 GPIO3B7_GPIO = 0, 368 GPIO3B7_MAC_RXD0 = (1 << GPIO3B7_SHIFT), 369 370 GPIO3B6_SHIFT = 12, 371 GPIO3B6_MASK = GENMASK(GPIO3B6_SHIFT + 1, GPIO3B6_SHIFT), 372 GPIO3B6_GPIO = 0, 373 GPIO3B6_MAC_TXD3 = (1 << GPIO3B6_SHIFT), 374 375 GPIO3B5_SHIFT = 10, 376 GPIO3B5_MASK = GENMASK(GPIO3B5_SHIFT + 1, GPIO3B5_SHIFT), 377 GPIO3B5_GPIO = 0, 378 GPIO3B5_MAC_TXEN = (1 << GPIO3B5_SHIFT), 379 380 GPIO3B4_SHIFT = 8, 381 GPIO3B4_MASK = GENMASK(GPIO3B4_SHIFT + 1, GPIO3B4_SHIFT), 382 GPIO3B4_GPIO = 0, 383 GPIO3B4_MAC_COL = (1 << GPIO3B4_SHIFT), 384 385 GPIO3B3_SHIFT = 6, 386 GPIO3B3_MASK = GENMASK(GPIO3B3_SHIFT + 1, GPIO3B3_SHIFT), 387 GPIO3B3_GPIO = 0, 388 GPIO3B3_MAC_CRS = (1 << GPIO3B3_SHIFT), 389 390 GPIO3B2_SHIFT = 4, 391 GPIO3B2_MASK = GENMASK(GPIO3B2_SHIFT + 1, GPIO3B2_SHIFT), 392 GPIO3B2_GPIO = 0, 393 GPIO3B2_MAC_TXD2 = (1 << GPIO3B2_SHIFT), 394 395 GPIO3B1_SHIFT = 2, 396 GPIO3B1_MASK = GENMASK(GPIO3B1_SHIFT + 1, GPIO3B1_SHIFT), 397 GPIO3B1_GPIO = 0, 398 GPIO3B1_MAC_TXD1 = (1 << GPIO3B1_SHIFT), 399 400 GPIO3B0_SHIFT = 0, 401 GPIO3B0_MASK = GENMASK(GPIO3B0_SHIFT + 1, GPIO3B0_SHIFT), 402 GPIO3B0_GPIO = 0, 403 GPIO3B0_MAC_TXD0 = (1 << GPIO3B0_SHIFT), 404 GPIO3B0_PWM0 = (2 << GPIO3B0_SHIFT), 405 }; 406 407 /*GRF_GPIO3C_IOMUX*/ 408 enum { 409 GPIO3C6_SHIFT = 12, 410 GPIO3C6_MASK = GENMASK(GPIO3C6_SHIFT + 1, GPIO3C6_SHIFT), 411 GPIO3C6_GPIO = 0, 412 GPIO3C6_MAC_CLK = (1 << GPIO3C6_SHIFT), 413 414 GPIO3C5_SHIFT = 10, 415 GPIO3C5_MASK = GENMASK(GPIO3C5_SHIFT + 1, GPIO3C5_SHIFT), 416 GPIO3C5_GPIO = 0, 417 GPIO3C5_MAC_RXEN = (1 << GPIO3C5_SHIFT), 418 419 GPIO3C4_SHIFT = 8, 420 GPIO3C4_MASK = GENMASK(GPIO3C4_SHIFT + 1, GPIO3C4_SHIFT), 421 GPIO3C4_GPIO = 0, 422 GPIO3C4_MAC_RXDV = (1 << GPIO3C4_SHIFT), 423 424 GPIO3C3_SHIFT = 6, 425 GPIO3C3_MASK = GENMASK(GPIO3C3_SHIFT + 1, GPIO3C3_SHIFT), 426 GPIO3C3_GPIO = 0, 427 GPIO3C3_MAC_MDC = (1 << GPIO3C3_SHIFT), 428 429 GPIO3C2_SHIFT = 4, 430 GPIO3C2_MASK = GENMASK(GPIO3C2_SHIFT + 1, GPIO3C2_SHIFT), 431 GPIO3C2_GPIO = 0, 432 GPIO3C2_MAC_RXD3 = (1 << GPIO3C2_SHIFT), 433 434 GPIO3C1_SHIFT = 2, 435 GPIO3C1_MASK = GENMASK(GPIO3C1_SHIFT + 1, GPIO3C1_SHIFT), 436 GPIO3C1_GPIO = 0, 437 GPIO3C1_MAC_RXD2 = (1 << GPIO3C1_SHIFT), 438 439 GPIO3C0_SHIFT = 0, 440 GPIO3C0_MASK = GENMASK(GPIO3C0_SHIFT + 1, GPIO3C0_SHIFT), 441 GPIO3C0_GPIO = 0, 442 GPIO3C0_MAC_RXD1 = (1 << GPIO3C0_SHIFT), 443 }; 444 445 /*GRF_GPIO3D_IOMUX*/ 446 enum { 447 GPIO3D4_SHIFT = 8, 448 GPIO3D4_MASK = GENMASK(GPIO3D4_SHIFT + 1, GPIO3D4_SHIFT), 449 GPIO3D4_GPIO = 0, 450 GPIO3D4_MAC_TXCLK = (1 << GPIO3D4_SHIFT), 451 GPIO3D4_SPI1_CNS1 = (2 << GPIO3D4_SHIFT), 452 453 GPIO3D1_SHIFT = 2, 454 GPIO3D1_MASK = GENMASK(GPIO3D1_SHIFT + 1, GPIO3D1_SHIFT), 455 GPIO3D1_GPIO = 0, 456 GPIO3D1_MAC_RXCLK = (1 << GPIO3D1_SHIFT), 457 458 GPIO3D0_SHIFT = 0, 459 GPIO3D0_MASK = GENMASK(GPIO3D0_SHIFT + 1, GPIO3D0_SHIFT), 460 GPIO3D0_GPIO = 0, 461 GPIO3D0_MAC_MDIO = (1 << GPIO3D0_SHIFT), 462 }; 463 464 struct rk3368_pinctrl_priv { 465 struct rk3368_grf *grf; 466 struct rk3368_pmu_grf *pmugrf; 467 }; 468 469 static void pinctrl_rk3368_uart_config(struct rk3368_pinctrl_priv *priv, 470 int uart_id) 471 { 472 struct rk3368_grf *grf = priv->grf; 473 struct rk3368_pmu_grf *pmugrf = priv->pmugrf; 474 475 switch (uart_id) { 476 case PERIPH_ID_UART2: 477 rk_clrsetreg(&grf->gpio2a_iomux, 478 GPIO2A6_MASK | GPIO2A5_MASK, 479 GPIO2A6_UART2_SIN | GPIO2A5_UART2_SOUT); 480 break; 481 case PERIPH_ID_UART0: 482 break; 483 case PERIPH_ID_UART1: 484 break; 485 case PERIPH_ID_UART3: 486 break; 487 case PERIPH_ID_UART4: 488 rk_clrsetreg(&pmugrf->gpio0d_iomux, 489 GPIO0D0_MASK | GPIO0D1_MASK | 490 GPIO0D2_MASK | GPIO0D3_MASK, 491 GPIO0D0_GPIO | GPIO0D1_GPIO | 492 GPIO0D2_UART4_SOUT | GPIO0D3_UART4_SIN); 493 break; 494 default: 495 debug("uart id = %d iomux error!\n", uart_id); 496 break; 497 } 498 } 499 500 static void pinctrl_rk3368_spi_config(struct rk3368_pinctrl_priv *priv, 501 int spi_id) 502 { 503 struct rk3368_grf *grf = priv->grf; 504 struct rk3368_pmu_grf *pmugrf = priv->pmugrf; 505 506 switch (spi_id) { 507 case PERIPH_ID_SPI0: 508 /* 509 * eMMC can only be connected with 4 bits, when SPI0 is used. 510 * This is all-or-nothing, so we assume that if someone asks us 511 * to configure SPI0, that their eMMC interface is unused or 512 * configured appropriately. 513 */ 514 rk_clrsetreg(&grf->gpio1d_iomux, 515 GPIO1D0_MASK | GPIO1D1_MASK | 516 GPIO1D5_MASK, 517 GPIO1D0_SPI0_CSN0 | GPIO1D1_SPI0_CSN1 | 518 GPIO1D5_SPI0_CLK); 519 rk_clrsetreg(&grf->gpio1c_iomux, 520 GPIO1C6_MASK | GPIO1C7_MASK, 521 GPIO1C6_SPI0_RXD | GPIO1C7_SPI0_TXD); 522 break; 523 case PERIPH_ID_SPI1: 524 /* 525 * We don't implement support for configuring SPI1_CSN#1, as it 526 * conflicts with the GMAC (MAC TX clk-out). 527 */ 528 rk_clrsetreg(&grf->gpio1b_iomux, 529 GPIO1B6_MASK | GPIO1B7_MASK, 530 GPIO1B6_SPI1_CLK | GPIO1B7_SPI1_CSN0); 531 rk_clrsetreg(&grf->gpio1c_iomux, 532 GPIO1C0_MASK | GPIO1C1_MASK, 533 GPIO1C0_SPI1_TXD | GPIO1C1_SPI1_RXD); 534 break; 535 case PERIPH_ID_SPI2: 536 rk_clrsetreg(&pmugrf->gpio0b_iomux, 537 GPIO0B2_MASK | GPIO0B3_MASK | 538 GPIO0B4_MASK | GPIO0B5_MASK, 539 GPIO0B2_SPI2_RXD | GPIO0B3_SPI2_TXD | 540 GPIO0B4_SPI2_CLK | GPIO0B5_SPI2_CSN0); 541 break; 542 default: 543 debug("%s: spi id = %d iomux error!\n", __func__, spi_id); 544 break; 545 } 546 } 547 548 #if CONFIG_IS_ENABLED(GMAC_ROCKCHIP) 549 static void pinctrl_rk3368_gmac_config(struct rk3368_grf *grf, int gmac_id) 550 { 551 rk_clrsetreg(&grf->gpio3b_iomux, 552 GPIO3B0_MASK | GPIO3B1_MASK | 553 GPIO3B2_MASK | GPIO3B5_MASK | 554 GPIO3B6_MASK | GPIO3B7_MASK, 555 GPIO3B0_MAC_TXD0 | GPIO3B1_MAC_TXD1 | 556 GPIO3B2_MAC_TXD2 | GPIO3B5_MAC_TXEN | 557 GPIO3B6_MAC_TXD3 | GPIO3B7_MAC_RXD0); 558 rk_clrsetreg(&grf->gpio3c_iomux, 559 GPIO3C0_MASK | GPIO3C1_MASK | 560 GPIO3C2_MASK | GPIO3C3_MASK | 561 GPIO3C4_MASK | GPIO3C5_MASK | 562 GPIO3C6_MASK, 563 GPIO3C0_MAC_RXD1 | GPIO3C1_MAC_RXD2 | 564 GPIO3C2_MAC_RXD3 | GPIO3C3_MAC_MDC | 565 GPIO3C4_MAC_RXDV | GPIO3C5_MAC_RXEN | 566 GPIO3C6_MAC_CLK); 567 rk_clrsetreg(&grf->gpio3d_iomux, 568 GPIO3D0_MASK | GPIO3D1_MASK | 569 GPIO3D4_MASK, 570 GPIO3D0_MAC_MDIO | GPIO3D1_MAC_RXCLK | 571 GPIO3D4_MAC_TXCLK); 572 } 573 #endif 574 575 static void pinctrl_rk3368_sdmmc_config(struct rk3368_grf *grf, int mmc_id) 576 { 577 switch (mmc_id) { 578 case PERIPH_ID_EMMC: 579 debug("mmc id = %d setting registers!\n", mmc_id); 580 rk_clrsetreg(&grf->gpio1c_iomux, 581 GPIO1C2_MASK | GPIO1C3_MASK | 582 GPIO1C4_MASK | GPIO1C5_MASK | 583 GPIO1C6_MASK | GPIO1C7_MASK, 584 GPIO1C2_EMMC_DATA0 | 585 GPIO1C3_EMMC_DATA1 | 586 GPIO1C4_EMMC_DATA2 | 587 GPIO1C5_EMMC_DATA3 | 588 GPIO1C6_EMMC_DATA4 | 589 GPIO1C7_EMMC_DATA5); 590 rk_clrsetreg(&grf->gpio1d_iomux, 591 GPIO1D0_MASK | GPIO1D1_MASK | 592 GPIO1D2_MASK | GPIO1D3_MASK, 593 GPIO1D0_EMMC_DATA6 | 594 GPIO1D1_EMMC_DATA7 | 595 GPIO1D2_EMMC_CMD | 596 GPIO1D3_EMMC_PWREN); 597 rk_clrsetreg(&grf->gpio2a_iomux, 598 GPIO2A3_MASK | GPIO2A4_MASK, 599 GPIO2A3_EMMC_RSTNOUT | 600 GPIO2A4_EMMC_CLKOUT); 601 break; 602 case PERIPH_ID_SDCARD: 603 debug("mmc id = %d setting registers!\n", mmc_id); 604 rk_clrsetreg(&grf->gpio2a_iomux, 605 GPIO2A5_MASK | GPIO2A7_MASK | 606 GPIO2A7_MASK, 607 GPIO2A5_SDMMC0_D0 | GPIO2A6_SDMMC0_D1 | 608 GPIO2A7_SDMMC0_D2); 609 rk_clrsetreg(&grf->gpio2b_iomux, 610 GPIO2B0_MASK | GPIO2B1_MASK | 611 GPIO2B2_MASK | GPIO2B3_MASK, 612 GPIO2B0_SDMMC0_D3 | GPIO2B1_SDMMC0_CLKOUT | 613 GPIO2B2_SDMMC0_CMD | GPIO2B3_SDMMC0_DTECTN); 614 break; 615 default: 616 debug("mmc id = %d iomux error!\n", mmc_id); 617 break; 618 } 619 } 620 621 static int rk3368_pinctrl_request(struct udevice *dev, int func, int flags) 622 { 623 struct rk3368_pinctrl_priv *priv = dev_get_priv(dev); 624 625 debug("%s: func=%d, flags=%x\n", __func__, func, flags); 626 switch (func) { 627 case PERIPH_ID_UART0: 628 case PERIPH_ID_UART1: 629 case PERIPH_ID_UART2: 630 case PERIPH_ID_UART3: 631 case PERIPH_ID_UART4: 632 pinctrl_rk3368_uart_config(priv, func); 633 break; 634 case PERIPH_ID_SPI0: 635 case PERIPH_ID_SPI1: 636 case PERIPH_ID_SPI2: 637 pinctrl_rk3368_spi_config(priv, func); 638 break; 639 case PERIPH_ID_EMMC: 640 case PERIPH_ID_SDCARD: 641 pinctrl_rk3368_sdmmc_config(priv->grf, func); 642 break; 643 #if CONFIG_IS_ENABLED(GMAC_ROCKCHIP) 644 case PERIPH_ID_GMAC: 645 pinctrl_rk3368_gmac_config(priv->grf, func); 646 break; 647 #endif 648 default: 649 return -EINVAL; 650 } 651 652 return 0; 653 } 654 655 static int rk3368_pinctrl_get_periph_id(struct udevice *dev, 656 struct udevice *periph) 657 { 658 u32 cell[3]; 659 int ret; 660 661 ret = dev_read_u32_array(periph, "interrupts", cell, ARRAY_SIZE(cell)); 662 if (ret < 0) 663 return -EINVAL; 664 665 switch (cell[1]) { 666 case 59: 667 return PERIPH_ID_UART4; 668 case 58: 669 return PERIPH_ID_UART3; 670 case 57: 671 return PERIPH_ID_UART2; 672 case 56: 673 return PERIPH_ID_UART1; 674 case 55: 675 return PERIPH_ID_UART0; 676 case 44: 677 return PERIPH_ID_SPI0; 678 case 45: 679 return PERIPH_ID_SPI1; 680 case 41: 681 return PERIPH_ID_SPI2; 682 case 35: 683 return PERIPH_ID_EMMC; 684 case 32: 685 return PERIPH_ID_SDCARD; 686 #if CONFIG_IS_ENABLED(GMAC_ROCKCHIP) 687 case 27: 688 return PERIPH_ID_GMAC; 689 #endif 690 } 691 692 return -ENOENT; 693 } 694 695 static int rk3368_pinctrl_set_state_simple(struct udevice *dev, 696 struct udevice *periph) 697 { 698 int func; 699 700 func = rk3368_pinctrl_get_periph_id(dev, periph); 701 if (func < 0) 702 return func; 703 704 return rk3368_pinctrl_request(dev, func, 0); 705 } 706 707 static struct pinctrl_ops rk3368_pinctrl_ops = { 708 .set_state_simple = rk3368_pinctrl_set_state_simple, 709 .request = rk3368_pinctrl_request, 710 .get_periph_id = rk3368_pinctrl_get_periph_id, 711 }; 712 713 static int rk3368_pinctrl_probe(struct udevice *dev) 714 { 715 struct rk3368_pinctrl_priv *priv = dev_get_priv(dev); 716 int ret = 0; 717 718 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 719 priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); 720 721 debug("%s: grf=%p pmugrf:%p\n", __func__, priv->grf, priv->pmugrf); 722 723 return ret; 724 } 725 726 static const struct udevice_id rk3368_pinctrl_ids[] = { 727 { .compatible = "rockchip,rk3368-pinctrl" }, 728 { } 729 }; 730 731 U_BOOT_DRIVER(pinctrl_rk3368) = { 732 .name = "rockchip_rk3368_pinctrl", 733 .id = UCLASS_PINCTRL, 734 .of_match = rk3368_pinctrl_ids, 735 .priv_auto_alloc_size = sizeof(struct rk3368_pinctrl_priv), 736 .ops = &rk3368_pinctrl_ops, 737 .bind = dm_scan_fdt_dev, 738 .probe = rk3368_pinctrl_probe, 739 }; 740
