1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * SH SPI driver 4 * 5 * Copyright (C) 2011-2012 Renesas Solutions Corp. 6 */ 7 8 #include <common.h> 9 #include <console.h> 10 #include <malloc.h> 11 #include <spi.h> 12 #include <asm/io.h> 13 #include "sh_spi.h" 14 15 static void sh_spi_write(unsigned long data, unsigned long *reg) 16 { 17 writel(data, reg); 18 } 19 20 static unsigned long sh_spi_read(unsigned long *reg) 21 { 22 return readl(reg); 23 } 24 25 static void sh_spi_set_bit(unsigned long val, unsigned long *reg) 26 { 27 unsigned long tmp; 28 29 tmp = sh_spi_read(reg); 30 tmp |= val; 31 sh_spi_write(tmp, reg); 32 } 33 34 static void sh_spi_clear_bit(unsigned long val, unsigned long *reg) 35 { 36 unsigned long tmp; 37 38 tmp = sh_spi_read(reg); 39 tmp &= ~val; 40 sh_spi_write(tmp, reg); 41 } 42 43 static void clear_fifo(struct sh_spi *ss) 44 { 45 sh_spi_set_bit(SH_SPI_RSTF, &ss->regs->cr2); 46 sh_spi_clear_bit(SH_SPI_RSTF, &ss->regs->cr2); 47 } 48 49 static int recvbuf_wait(struct sh_spi *ss) 50 { 51 while (sh_spi_read(&ss->regs->cr1) & SH_SPI_RBE) { 52 if (ctrlc()) 53 return 1; 54 udelay(10); 55 } 56 return 0; 57 } 58 59 static int write_fifo_empty_wait(struct sh_spi *ss) 60 { 61 while (!(sh_spi_read(&ss->regs->cr1) & SH_SPI_TBE)) { 62 if (ctrlc()) 63 return 1; 64 udelay(10); 65 } 66 return 0; 67 } 68 69 void spi_init(void) 70 { 71 } 72 73 static void sh_spi_set_cs(struct sh_spi *ss, unsigned int cs) 74 { 75 unsigned long val = 0; 76 77 if (cs & 0x01) 78 val |= SH_SPI_SSS0; 79 if (cs & 0x02) 80 val |= SH_SPI_SSS1; 81 82 sh_spi_clear_bit(SH_SPI_SSS0 | SH_SPI_SSS1, &ss->regs->cr4); 83 sh_spi_set_bit(val, &ss->regs->cr4); 84 } 85 86 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, 87 unsigned int max_hz, unsigned int mode) 88 { 89 struct sh_spi *ss; 90 91 if (!spi_cs_is_valid(bus, cs)) 92 return NULL; 93 94 ss = spi_alloc_slave(struct sh_spi, bus, cs); 95 if (!ss) 96 return NULL; 97 98 ss->regs = (struct sh_spi_regs *)CONFIG_SH_SPI_BASE; 99 100 /* SPI sycle stop */ 101 sh_spi_write(0xfe, &ss->regs->cr1); 102 /* CR1 init */ 103 sh_spi_write(0x00, &ss->regs->cr1); 104 /* CR3 init */ 105 sh_spi_write(0x00, &ss->regs->cr3); 106 sh_spi_set_cs(ss, cs); 107 108 clear_fifo(ss); 109 110 /* 1/8 clock */ 111 sh_spi_write(sh_spi_read(&ss->regs->cr2) | 0x07, &ss->regs->cr2); 112 udelay(10); 113 114 return &ss->slave; 115 } 116 117 void spi_free_slave(struct spi_slave *slave) 118 { 119 struct sh_spi *spi = to_sh_spi(slave); 120 121 free(spi); 122 } 123 124 int spi_claim_bus(struct spi_slave *slave) 125 { 126 return 0; 127 } 128 129 void spi_release_bus(struct spi_slave *slave) 130 { 131 struct sh_spi *ss = to_sh_spi(slave); 132 133 sh_spi_write(sh_spi_read(&ss->regs->cr1) & 134 ~(SH_SPI_SSA | SH_SPI_SSDB | SH_SPI_SSD), &ss->regs->cr1); 135 } 136 137 static int sh_spi_send(struct sh_spi *ss, const unsigned char *tx_data, 138 unsigned int len, unsigned long flags) 139 { 140 int i, cur_len, ret = 0; 141 int remain = (int)len; 142 143 if (len >= SH_SPI_FIFO_SIZE) 144 sh_spi_set_bit(SH_SPI_SSA, &ss->regs->cr1); 145 146 while (remain > 0) { 147 cur_len = (remain < SH_SPI_FIFO_SIZE) ? 148 remain : SH_SPI_FIFO_SIZE; 149 for (i = 0; i < cur_len && 150 !(sh_spi_read(&ss->regs->cr4) & SH_SPI_WPABRT) && 151 !(sh_spi_read(&ss->regs->cr1) & SH_SPI_TBF); 152 i++) 153 sh_spi_write(tx_data[i], &ss->regs->tbr_rbr); 154 155 cur_len = i; 156 157 if (sh_spi_read(&ss->regs->cr4) & SH_SPI_WPABRT) { 158 /* Abort the transaction */ 159 flags |= SPI_XFER_END; 160 sh_spi_set_bit(SH_SPI_WPABRT, &ss->regs->cr4); 161 ret = 1; 162 break; 163 } 164 165 remain -= cur_len; 166 tx_data += cur_len; 167 168 if (remain > 0) 169 write_fifo_empty_wait(ss); 170 } 171 172 if (flags & SPI_XFER_END) { 173 sh_spi_clear_bit(SH_SPI_SSD | SH_SPI_SSDB, &ss->regs->cr1); 174 sh_spi_set_bit(SH_SPI_SSA, &ss->regs->cr1); 175 udelay(100); 176 write_fifo_empty_wait(ss); 177 } 178 179 return ret; 180 } 181 182 static int sh_spi_receive(struct sh_spi *ss, unsigned char *rx_data, 183 unsigned int len, unsigned long flags) 184 { 185 int i; 186 187 if (len > SH_SPI_MAX_BYTE) 188 sh_spi_write(SH_SPI_MAX_BYTE, &ss->regs->cr3); 189 else 190 sh_spi_write(len, &ss->regs->cr3); 191 192 sh_spi_clear_bit(SH_SPI_SSD | SH_SPI_SSDB, &ss->regs->cr1); 193 sh_spi_set_bit(SH_SPI_SSA, &ss->regs->cr1); 194 195 for (i = 0; i < len; i++) { 196 if (recvbuf_wait(ss)) 197 return 0; 198 199 rx_data[i] = (unsigned char)sh_spi_read(&ss->regs->tbr_rbr); 200 } 201 sh_spi_write(0, &ss->regs->cr3); 202 203 return 0; 204 } 205 206 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, 207 void *din, unsigned long flags) 208 { 209 struct sh_spi *ss = to_sh_spi(slave); 210 const unsigned char *tx_data = dout; 211 unsigned char *rx_data = din; 212 unsigned int len = bitlen / 8; 213 int ret = 0; 214 215 if (flags & SPI_XFER_BEGIN) 216 sh_spi_write(sh_spi_read(&ss->regs->cr1) & ~SH_SPI_SSA, 217 &ss->regs->cr1); 218 219 if (tx_data) 220 ret = sh_spi_send(ss, tx_data, len, flags); 221 222 if (ret == 0 && rx_data) 223 ret = sh_spi_receive(ss, rx_data, len, flags); 224 225 if (flags & SPI_XFER_END) { 226 sh_spi_set_bit(SH_SPI_SSD, &ss->regs->cr1); 227 udelay(100); 228 229 sh_spi_clear_bit(SH_SPI_SSA | SH_SPI_SSDB | SH_SPI_SSD, 230 &ss->regs->cr1); 231 clear_fifo(ss); 232 } 233 234 return ret; 235 } 236 237 int spi_cs_is_valid(unsigned int bus, unsigned int cs) 238 { 239 if (!bus && cs < SH_SPI_NUM_CS) 240 return 1; 241 else 242 return 0; 243 } 244 245 void spi_cs_activate(struct spi_slave *slave) 246 { 247 248 } 249 250 void spi_cs_deactivate(struct spi_slave *slave) 251 { 252 253 } 254
