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      1 /* SPDX-License-Identifier: GPL-2.0+ */
      2 /* linux/arch/arm/plat-s3c/include/plat/regs-otg.h
      3  *
      4  * Copyright (C) 2004 Herbert Poetzl <herbert (at) 13thfloor.at>
      5  *
      6  * Registers remapping:
      7  * Lukasz Majewski <l.majewski (at) samsumg.com>
      8  */
      9 
     10 #ifndef __ASM_ARCH_REGS_USB_OTG_HS_H
     11 #define __ASM_ARCH_REGS_USB_OTG_HS_H
     12 
     13 /* USB2.0 OTG Controller register */
     14 struct dwc2_usbotg_phy {
     15 	u32 phypwr;
     16 	u32 phyclk;
     17 	u32 rstcon;
     18 };
     19 
     20 /* Device Logical IN Endpoint-Specific Registers */
     21 struct dwc2_dev_in_endp {
     22 	u32 diepctl;
     23 	u8  res1[4];
     24 	u32 diepint;
     25 	u8  res2[4];
     26 	u32 dieptsiz;
     27 	u32 diepdma;
     28 	u8  res3[4];
     29 	u32 diepdmab;
     30 };
     31 
     32 /* Device Logical OUT Endpoint-Specific Registers */
     33 struct dwc2_dev_out_endp {
     34 	u32 doepctl;
     35 	u8  res1[4];
     36 	u32 doepint;
     37 	u8  res2[4];
     38 	u32 doeptsiz;
     39 	u32 doepdma;
     40 	u8  res3[4];
     41 	u32 doepdmab;
     42 };
     43 
     44 struct ep_fifo {
     45 	u32 fifo;
     46 	u8  res[4092];
     47 };
     48 
     49 /* USB2.0 OTG Controller register */
     50 struct dwc2_usbotg_reg {
     51 	/* Core Global Registers */
     52 	u32 gotgctl; /* OTG Control & Status */
     53 	u32 gotgint; /* OTG Interrupt */
     54 	u32 gahbcfg; /* Core AHB Configuration */
     55 	u32 gusbcfg; /* Core USB Configuration */
     56 	u32 grstctl; /* Core Reset */
     57 	u32 gintsts; /* Core Interrupt */
     58 	u32 gintmsk; /* Core Interrupt Mask */
     59 	u32 grxstsr; /* Receive Status Debug Read/Status Read */
     60 	u32 grxstsp; /* Receive Status Debug Pop/Status Pop */
     61 	u32 grxfsiz; /* Receive FIFO Size */
     62 	u32 gnptxfsiz; /* Non-Periodic Transmit FIFO Size */
     63 	u8  res1[216];
     64 	u32 dieptxf[15]; /* Device Periodic Transmit FIFO size register */
     65 	u8  res2[1728];
     66 	/* Device Configuration */
     67 	u32 dcfg; /* Device Configuration Register */
     68 	u32 dctl; /* Device Control */
     69 	u32 dsts; /* Device Status */
     70 	u8  res3[4];
     71 	u32 diepmsk; /* Device IN Endpoint Common Interrupt Mask */
     72 	u32 doepmsk; /* Device OUT Endpoint Common Interrupt Mask */
     73 	u32 daint; /* Device All Endpoints Interrupt */
     74 	u32 daintmsk; /* Device All Endpoints Interrupt Mask */
     75 	u8  res4[224];
     76 	struct dwc2_dev_in_endp in_endp[16];
     77 	struct dwc2_dev_out_endp out_endp[16];
     78 	u8  res5[768];
     79 	struct ep_fifo ep[16];
     80 };
     81 
     82 /*===================================================================== */
     83 /*definitions related to CSR setting */
     84 
     85 /* DWC2_UDC_OTG_GOTGCTL */
     86 #define B_SESSION_VALID		(0x1<<19)
     87 #define A_SESSION_VALID		(0x1<<18)
     88 
     89 /* DWC2_UDC_OTG_GAHBCFG */
     90 #define PTXFE_HALF			(0<<8)
     91 #define PTXFE_ZERO			(1<<8)
     92 #define NPTXFE_HALF			(0<<7)
     93 #define NPTXFE_ZERO			(1<<7)
     94 #define MODE_SLAVE			(0<<5)
     95 #define MODE_DMA			(1<<5)
     96 #define BURST_SINGLE			(0<<1)
     97 #define BURST_INCR			(1<<1)
     98 #define BURST_INCR4			(3<<1)
     99 #define BURST_INCR8			(5<<1)
    100 #define BURST_INCR16			(7<<1)
    101 #define GBL_INT_UNMASK			(1<<0)
    102 #define GBL_INT_MASK			(0<<0)
    103 
    104 /* DWC2_UDC_OTG_GRSTCTL */
    105 #define AHB_MASTER_IDLE		(1u<<31)
    106 #define CORE_SOFT_RESET		(0x1<<0)
    107 
    108 /* DWC2_UDC_OTG_GINTSTS/DWC2_UDC_OTG_GINTMSK core interrupt register */
    109 #define INT_RESUME			(1u<<31)
    110 #define INT_DISCONN			(0x1<<29)
    111 #define INT_CONN_ID_STS_CNG		(0x1<<28)
    112 #define INT_OUT_EP			(0x1<<19)
    113 #define INT_IN_EP			(0x1<<18)
    114 #define INT_ENUMDONE			(0x1<<13)
    115 #define INT_RESET			(0x1<<12)
    116 #define INT_SUSPEND			(0x1<<11)
    117 #define INT_EARLY_SUSPEND		(0x1<<10)
    118 #define INT_NP_TX_FIFO_EMPTY		(0x1<<5)
    119 #define INT_RX_FIFO_NOT_EMPTY		(0x1<<4)
    120 #define INT_SOF			(0x1<<3)
    121 #define INT_DEV_MODE			(0x0<<0)
    122 #define INT_HOST_MODE			(0x1<<1)
    123 #define INT_GOUTNakEff			(0x01<<7)
    124 #define INT_GINNakEff			(0x01<<6)
    125 
    126 #define FULL_SPEED_CONTROL_PKT_SIZE	8
    127 #define FULL_SPEED_BULK_PKT_SIZE	64
    128 
    129 #define HIGH_SPEED_CONTROL_PKT_SIZE	64
    130 #define HIGH_SPEED_BULK_PKT_SIZE	512
    131 
    132 #define RX_FIFO_SIZE			(1024)
    133 #define NPTX_FIFO_SIZE			(1024)
    134 #define PTX_FIFO_SIZE			(384)
    135 
    136 #define DEPCTL_TXFNUM_0		(0x0<<22)
    137 #define DEPCTL_TXFNUM_1		(0x1<<22)
    138 #define DEPCTL_TXFNUM_2		(0x2<<22)
    139 #define DEPCTL_TXFNUM_3		(0x3<<22)
    140 #define DEPCTL_TXFNUM_4		(0x4<<22)
    141 
    142 /* Enumeration speed */
    143 #define USB_HIGH_30_60MHZ		(0x0<<1)
    144 #define USB_FULL_30_60MHZ		(0x1<<1)
    145 #define USB_LOW_6MHZ			(0x2<<1)
    146 #define USB_FULL_48MHZ			(0x3<<1)
    147 
    148 /* DWC2_UDC_OTG_GRXSTSP STATUS */
    149 #define OUT_PKT_RECEIVED		(0x2<<17)
    150 #define OUT_TRANSFER_COMPLELTED	(0x3<<17)
    151 #define SETUP_TRANSACTION_COMPLETED	(0x4<<17)
    152 #define SETUP_PKT_RECEIVED		(0x6<<17)
    153 #define GLOBAL_OUT_NAK			(0x1<<17)
    154 
    155 /* DWC2_UDC_OTG_DCTL device control register */
    156 #define NORMAL_OPERATION		(0x1<<0)
    157 #define SOFT_DISCONNECT		(0x1<<1)
    158 
    159 /* DWC2_UDC_OTG_DAINT device all endpoint interrupt register */
    160 #define DAINT_OUT_BIT			(16)
    161 #define DAINT_MASK			(0xFFFF)
    162 
    163 /* DWC2_UDC_OTG_DIEPCTL0/DOEPCTL0 device
    164    control IN/OUT endpoint 0 control register */
    165 #define DEPCTL_EPENA			(0x1<<31)
    166 #define DEPCTL_EPDIS			(0x1<<30)
    167 #define DEPCTL_SETD1PID		(0x1<<29)
    168 #define DEPCTL_SETD0PID		(0x1<<28)
    169 #define DEPCTL_SNAK			(0x1<<27)
    170 #define DEPCTL_CNAK			(0x1<<26)
    171 #define DEPCTL_STALL			(0x1<<21)
    172 #define DEPCTL_TYPE_BIT		(18)
    173 #define DEPCTL_TYPE_MASK		(0x3<<18)
    174 #define DEPCTL_CTRL_TYPE		(0x0<<18)
    175 #define DEPCTL_ISO_TYPE		(0x1<<18)
    176 #define DEPCTL_BULK_TYPE		(0x2<<18)
    177 #define DEPCTL_INTR_TYPE		(0x3<<18)
    178 #define DEPCTL_USBACTEP		(0x1<<15)
    179 #define DEPCTL_NEXT_EP_BIT		(11)
    180 #define DEPCTL_MPS_BIT			(0)
    181 #define DEPCTL_MPS_MASK		(0x7FF)
    182 
    183 #define DEPCTL0_MPS_64			(0x0<<0)
    184 #define DEPCTL0_MPS_32			(0x1<<0)
    185 #define DEPCTL0_MPS_16			(0x2<<0)
    186 #define DEPCTL0_MPS_8			(0x3<<0)
    187 #define DEPCTL_MPS_BULK_512		(512<<0)
    188 #define DEPCTL_MPS_INT_MPS_16		(16<<0)
    189 
    190 #define DIEPCTL0_NEXT_EP_BIT		(11)
    191 
    192 
    193 /* DWC2_UDC_OTG_DIEPMSK/DOEPMSK device IN/OUT endpoint
    194    common interrupt mask register */
    195 /* DWC2_UDC_OTG_DIEPINTn/DOEPINTn device IN/OUT endpoint interrupt register */
    196 #define BACK2BACK_SETUP_RECEIVED	(0x1<<6)
    197 #define INTKNEPMIS			(0x1<<5)
    198 #define INTKN_TXFEMP			(0x1<<4)
    199 #define NON_ISO_IN_EP_TIMEOUT		(0x1<<3)
    200 #define CTRL_OUT_EP_SETUP_PHASE_DONE	(0x1<<3)
    201 #define AHB_ERROR			(0x1<<2)
    202 #define EPDISBLD			(0x1<<1)
    203 #define TRANSFER_DONE			(0x1<<0)
    204 
    205 #define USB_PHY_CTRL_EN0                (0x1 << 0)
    206 
    207 /* OPHYPWR */
    208 #define PHY_0_SLEEP                     (0x1 << 5)
    209 #define OTG_DISABLE_0                   (0x1 << 4)
    210 #define ANALOG_PWRDOWN                  (0x1 << 3)
    211 #define FORCE_SUSPEND_0                 (0x1 << 0)
    212 
    213 /* URSTCON */
    214 #define HOST_SW_RST                     (0x1 << 4)
    215 #define PHY_SW_RST1                     (0x1 << 3)
    216 #define PHYLNK_SW_RST                   (0x1 << 2)
    217 #define LINK_SW_RST                     (0x1 << 1)
    218 #define PHY_SW_RST0                     (0x1 << 0)
    219 
    220 /* OPHYCLK */
    221 #define COMMON_ON_N1                    (0x1 << 7)
    222 #define COMMON_ON_N0                    (0x1 << 4)
    223 #define ID_PULLUP0                      (0x1 << 2)
    224 #define CLK_SEL_24MHZ                   (0x3 << 0)
    225 #define CLK_SEL_12MHZ                   (0x2 << 0)
    226 #define CLK_SEL_48MHZ                   (0x0 << 0)
    227 
    228 #define EXYNOS4X12_ID_PULLUP0		(0x01 << 3)
    229 #define EXYNOS4X12_COMMON_ON_N0	(0x01 << 4)
    230 #define EXYNOS4X12_CLK_SEL_12MHZ	(0x02 << 0)
    231 #define EXYNOS4X12_CLK_SEL_24MHZ	(0x05 << 0)
    232 
    233 /* Device Configuration Register DCFG */
    234 #define DEV_SPEED_HIGH_SPEED_20         (0x0 << 0)
    235 #define DEV_SPEED_FULL_SPEED_20         (0x1 << 0)
    236 #define DEV_SPEED_LOW_SPEED_11          (0x2 << 0)
    237 #define DEV_SPEED_FULL_SPEED_11         (0x3 << 0)
    238 #define EP_MISS_CNT(x)                  (x << 18)
    239 #define DEVICE_ADDRESS(x)               (x << 4)
    240 
    241 /* Core Reset Register (GRSTCTL) */
    242 #define TX_FIFO_FLUSH                   (0x1 << 5)
    243 #define RX_FIFO_FLUSH                   (0x1 << 4)
    244 #define TX_FIFO_NUMBER(x)               (x << 6)
    245 #define TX_FIFO_FLUSH_ALL               TX_FIFO_NUMBER(0x10)
    246 
    247 /* Masks definitions */
    248 #define GINTMSK_INIT	(INT_OUT_EP | INT_IN_EP | INT_RESUME | INT_ENUMDONE\
    249 			| INT_RESET | INT_SUSPEND)
    250 #define DOEPMSK_INIT	(CTRL_OUT_EP_SETUP_PHASE_DONE | AHB_ERROR|TRANSFER_DONE)
    251 #define DIEPMSK_INIT	(NON_ISO_IN_EP_TIMEOUT|AHB_ERROR|TRANSFER_DONE)
    252 #define GAHBCFG_INIT	(PTXFE_HALF | NPTXFE_HALF | MODE_DMA | BURST_INCR4\
    253 			| GBL_INT_UNMASK)
    254 
    255 /* Device Endpoint X Transfer Size Register (DIEPTSIZX) */
    256 #define DIEPT_SIZ_PKT_CNT(x)                      (x << 19)
    257 #define DIEPT_SIZ_XFER_SIZE(x)                    (x << 0)
    258 
    259 /* Device OUT Endpoint X Transfer Size Register (DOEPTSIZX) */
    260 #define DOEPT_SIZ_PKT_CNT(x)                      (x << 19)
    261 #define DOEPT_SIZ_XFER_SIZE(x)                    (x << 0)
    262 #define DOEPT_SIZ_XFER_SIZE_MAX_EP0               (0x7F << 0)
    263 #define DOEPT_SIZ_XFER_SIZE_MAX_EP                (0x7FFF << 0)
    264 
    265 /* Device Endpoint-N Control Register (DIEPCTLn/DOEPCTLn) */
    266 #define DIEPCTL_TX_FIFO_NUM(x)                    (x << 22)
    267 #define DIEPCTL_TX_FIFO_NUM_MASK                  (~DIEPCTL_TX_FIFO_NUM(0xF))
    268 
    269 /* Device ALL Endpoints Interrupt Register (DAINT) */
    270 #define DAINT_IN_EP_INT(x)                        (x << 0)
    271 #define DAINT_OUT_EP_INT(x)                       (x << 16)
    272 #endif
    273